公开(公告)号：US20120299072A1

公开(公告)日：2012-11-29

申请号：US13425906

申请日：2012-03-21

Applicant: WAN-DON KIM ,  Seung-Hwan Lee ,  Beom-Seok Kim ,  Kyu-Ho Cho ,  Oh-Seong Kwon ,  Geun-Kyu Choi ,  Ji-Eun Lim ,  Yong-Suk Tak

Inventor： WAN-DON KIM ,  Seung-Hwan Lee ,  Beom-Seok Kim ,  Kyu-Ho Cho ,  Oh-Seong Kwon ,  Geun-Kyu Choi ,  Ji-Eun Lim ,  Yong-Suk Tak

IPC: H01L27/06

CPC classification number: H01L21/823475 ,  H01L21/823456

Abstract: Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide.

Abstract translation: 提供了包括第一，第二和第三源极/漏极区域的半导体器件。 提供了与第一源/漏区接触的第一导电插塞，具有第一宽度和第一高度，并且包括第一材料。 设置覆盖第一导电插塞和基板的层间绝缘层。 提供垂直穿过层间绝缘层以与具有第二宽度和第二高度并且包括第二材料的第二源/漏区接触的第二导电插塞。 设置垂直贯穿层间绝缘层与第三源极/漏极区域接触的第三导电插塞，具有第三宽度和第三高度，并且包括第三材料。 第二种材料包括贵金属，贵金属氧化物或钙钛矿型导电氧化物。

公开(公告)号：US08319423B2

公开(公告)日：2012-11-27

申请号：US11637775

申请日：2006-12-13

Applicant: Kwang Su Lim ,  Jung Hwan Lee

Inventor： Kwang Su Lim ,  Jung Hwan Lee

IPC: H01J1/62 ,  H01J63/04

CPC classification number: H01L51/5259

Abstract: The present invention relates to a display device preventing a getter layer from contacting elements disposed in the display device, and an embodiment of the present invention may be achieved in a whole or in part by a display device comprising: A substrate; A pixel part disposed on the substrate; A cap comprising a first region attached on the substrate; and a second region having a position different from a position of the first region, connected with the first region, and corresponding to the pixel part; A getter layer disposed on the second region of the cap; and A protecting layer disposed on the getter layer.

Abstract translation: 本发明涉及一种防止吸气剂层与布置在显示装置中的元件接触的显示装置，本发明的一个实施例可以通过包括以下的显示装置全部或部分地实现：基板; 设置在基板上的像素部分; 一种帽，包括附接在所述基底上的第一区域; 以及第二区域，其具有与第一区域的位置不同的位置，与第一区域连接，并且对应于像素部分; 设置在盖的第二区域上的吸气剂层; 和设置在吸气剂层上的A保护层。

公开(公告)号：US08318558B2

公开(公告)日：2012-11-27

申请号：US12827845

申请日：2010-06-30

Applicant: Seung Hwan Lee

Inventor： Seung Hwan Lee

IPC: H01L21/8238

CPC classification number: H01L27/10885 ,  H01L21/743 ,  H01L27/10876 ,  H01L29/1083

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes vertical pillars formed by etching a semiconductor substrate and junction regions which are located among the neighboring vertical pillars and spaced apart from one another in a zigzag pattern. As a result, the semiconductor device easily guarantees an electrical passage between the semiconductor substrate and the vertical pillars, such that it substantially prevents the floating phenomenon from being generated, resulting in the prevention of deterioration of the semiconductor device.

Abstract translation: 公开了半导体器件及其形成方法。 半导体器件包括通过蚀刻半导体衬底和连接区域而形成的垂直柱，该区域位于相邻的垂直柱之间，并且以锯齿形图案彼此间隔开。 结果，半导体器件容易地保证半导体衬底和垂直柱之间的电通路，使得其基本上防止浮动现象被产生，从而防止半导体器件的劣化。

公开(公告)号：US20120294025A1

公开(公告)日：2012-11-22

申请号：US13475486

申请日：2012-05-18

Applicant: Hee Dong KIM ,  Moo Youn PARK ,  Soo Hwan LEE ,  Hee Seok PARK

Inventor： Hee Dong KIM ,  Moo Youn PARK ,  Soo Hwan LEE ,  Hee Seok PARK

IPC: F21V13/04 ,  H01L33/60

CPC classification number: F21S48/1388 ,  F21S41/143 ,  F21S41/16 ,  F21S41/255 ,  F21S41/32 ,  F21S41/323 ,  F21S41/37 ,  H01L33/44 ,  H01L33/46 ,  H01L33/50 ,  H01L33/501 ,  H01L33/507 ,  H01L33/60 ,  H01L2933/0091

Abstract: An LED assembly according to an embodiment of the present invention may improve dark regions generated between LED chips by employing a first reflective layer between the LED chips. By employing a transparent optical layer or an optical layer including a scattering particle between an LED chip and a phosphor layer, direct contact between the LED chip and the phosphor layer may be avoided, thereby preventing a low light extraction efficiency. Further, by employing a second reflection layer on side surfaces of an LED chip, an optical layer, and a phosphor layer, a relatively high contrast may be obtained. An LED assembly may enhance contrast through a reflective layer while increasing light extraction efficiency by including a scattering particle in a phosphor layer.

Abstract translation: 根据本发明的实施例的LED组件可以通过在LED芯片之间采用第一反射层来改善在LED芯片之间产生的暗区域。 通过在LED芯片和荧光体层之间采用透明光学层或包含散射粒子的光学层，可以避免LED芯片与荧光体层之间的直接接触，从而防止低的光提取效率。 此外，通过在LED芯片，光学层和荧光体层的侧表面上采用第二反射层，可以获得相对较高的对比度。 LED组件可以通过反射层增强对比度，同时通过在荧光体层中包括散射粒子来提高光提取效率。

公开(公告)号：US20120287672A1

公开(公告)日：2012-11-15

申请号：US13461494

申请日：2012-05-01

Applicant: Sang-Hwan LEE

Inventor： Sang-Hwan LEE

IPC: G09F13/18 ,  B32B37/14 ,  F21V13/02

CPC classification number: G02F1/133608 ,  G02F2202/28

Abstract: A backlight assembly includes a first light-emitting module, a light guide plate, a receiving container and a main adhesion member. The first light-emitting module includes a first circuit board including a first mounting surface, and a first light source on the first mounting surface. The light guide plate is on the first mounting surface and guides light from the first light source. The receiving container includes a bottom portion and receives the first light-emitting module and the light guide plate. The main adhesion member is between the first mounting surface and the light guide plate and is attached to the first circuit board and the light guide plate, and is between the light guide plate and the bottom portion and movable with respect to the light guide plate.

Abstract translation: 背光组件包括第一发光模块，导光板，接收容器和主粘合构件。 第一发光模块包括在第一安装表面上包括第一安装表面和第一光源的第一电路板。 导光板位于第一安装面上并引导来自第一光源的光。 接收容器包括底部并接收第一发光模块和导光板。 主粘合部件位于第一安装面和导光板之间，并且安装在第一电路板和导光板上，并且在导光板和底部之间，并相对于导光板可移动。

公开(公告)号：US08297084B2

公开(公告)日：2012-10-30

申请号：US12299195

申请日：2006-05-02

Applicant: Yong Suck Park ,  Ig Geun Kweun ,  Kyu Hwan Lee

Inventor： Yong Suck Park ,  Ig Geun Kweun ,  Kyu Hwan Lee

IPC: D06F37/00

CPC classification number: D06F37/00

Abstract: A drum washing machine is provided. The drum washing machine includes a tub that stores wash water therein, a drum rotatably mounted within the tub, a motor mounted in a rear of the tub, the motor having a shaft to rotate the drum, a bearing housing inserted into the tub having a hollow portion, which allows the shaft of the motor to pass therethrough, formed in a center thereof, a bearing secured to the hollow of the bearing housing, and an outlet hole that discharges gas or moisture generated in the bearing and a portion adjacent to the bearing outside of the bearing housing. The drum washing machine so constructed has enhanced durability, because it includes the outlet hole provided in the bearing housing where the shaft rotates that prevents moisture or water from remaining in the bearing housing.

Abstract translation: 提供滚筒洗衣机。 滚筒式洗衣机包括：储存洗涤水的桶，可旋转地安装在桶内的滚筒，安装在桶的后部的马达，马达具有用于旋转滚筒的轴;插入到桶中的轴承箱， 空心部分，其允许电机的轴穿过其形成在其中心，固定到轴承壳体的中空部的轴承以及排出在轴承中产生的气体或湿气的出口孔和与该轴承相邻的部分 轴承外部轴承座。 如此构造的滚筒洗衣机具有增强的耐久性，因为它包括设置在轴旋转的轴承壳体中的出口孔，防止水分或水残留在轴承壳体中。

公开(公告)号：US20120269010A1

公开(公告)日：2012-10-25

申请号：US13238435

申请日：2011-09-21

Applicant: Myung CHO ,  Seong-Je Park ,  Jung-Hwan Lee ,  Ji-Hwan Kim ,  Beom-Seok Hah

Inventor： Myung CHO ,  Seong-Je Park ,  Jung-Hwan Lee ,  Ji-Hwan Kim ,  Beom-Seok Hah

IPC: G11C7/06

CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C2211/5646

Abstract: A memory includes at least one first flag cell configured to store first flag data, at least one second flag cell configured to store second flag data, at least one first sensing node having a voltage level determined by the first flag data of the first flag cell, at least one second sensing having a voltage level determined by the second flag data of the second flag cell, a selection circuit configured to select the first sensing node or the second sensing node in response to a flag address; and a determination circuit having an internal node through which current corresponding to a voltage level of a selected sensing node flows and configured to determine a logic value of flag data corresponding to the selected sensing node among the first and second flag data by using an amount of current flowing through the internal node.

Abstract translation: 存储器包括被配置为存储第一标志数据的至少一个第一标志单元，被配置为存储第二标志数据的至少一个第二标志单元，具有由第一标志单元的第一标志数据确定的电压电平的至少一个第一感测节点 至少一个第二感测具有由第二标志单元的第二标志数据确定的电压电平，选择电路被配置为响应于标志地址选择第一感测节点或第二感测节点; 以及确定电路，其具有内部节点，通过所述内部节点流过与所选择的感测节点的电压电平相对应的电流，并且被配置为通过使用一定数量的第一和第二标志数据来确定与所选择的感测节点对应的标志数据的逻辑值 电流流过内部节点。

公开(公告)号：US08283958B2

公开(公告)日：2012-10-09

申请号：US12659010

申请日：2010-02-23

Applicant: Jong-Ryun Choi ,  Dong Hwan Lee ,  Su Ho Kim ,  Won Lee ,  Alex Joo ,  Ji Hun Oh

Inventor： Jong-Ryun Choi ,  Dong Hwan Lee ,  Su Ho Kim ,  Won Lee ,  Alex Joo ,  Ji Hun Oh

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/0805 ,  H03L7/0818 ,  H03L7/10

Abstract: A delay locked loop is provided. The delay locked loop controls the number of delay cells that delay the phase of an input clock during a locking operation and controls a phase delay value of at least one delay cell among a plurality of delay cells after the locking operation is completed.

Abstract translation: 提供延迟锁定环。 延迟锁定环控制在锁定操作期间延迟输入时钟的相位的延迟单元的数量，并且在锁定操作完成之后控制多个延迟单元中的至少一个延迟单元的相位延迟值。

公开(公告)号：US20120227872A1

公开(公告)日：2012-09-13

申请号：US13508745

申请日：2010-12-23

Applicant: Dong-Hyun Kim ,  You-Hwan Lee ,  Sang-Yoon Lee ,  Hyung-Keun Cho

Inventor： Dong-Hyun Kim ,  You-Hwan Lee ,  Sang-Yoon Lee ,  Hyung-Keun Cho

IPC: C21D9/52 ,  C22C38/12 ,  C22C38/04 ,  C22C38/02

CPC classification number: C22C38/12 ,  C21D8/065 ,  C21D9/0093 ,  C22C38/02 ,  C22C38/04

Abstract: An ultra-high-strength steel wire rod having excellent resistance to delayed fracture includes, by wt %, 0.7-1.2% C, 0.25-0.5% Si, 0.5-0.8% Mn, 0.02-0.1% V and a balance of Fe and inevitable impurities. The method includes the steps of heating the above steel composition to 1100° C. or lower and hot rolling at a temperature of 900-1000° C., followed by cooling to 600-650° C. at a prescribed rate, followed by cold drawing at a reduction ratio of 60-80%.

Abstract translation: 具有优异的延迟断裂性的超高强度钢线材包括：重量％，0.7-1.2％C，0.25-0.5％Si，0.5-0.8％Mn，0.02-0.1％V，余量为Fe和 不可避免的杂质。 该方法包括以下步骤：将上述钢组合物加热至1100℃以下，在900-1000℃的温度下进行热轧，然后以规定的比例冷却至600-650℃，然后冷却 以60-80％的减速比绘制。

公开(公告)号：US20120220115A1

公开(公告)日：2012-08-30

申请号：US13330057

申请日：2011-12-19

Applicant: Sul Hwan LEE

Inventor： Sul Hwan LEE

IPC: H01L21/28

CPC classification number: H01L29/4236 ,  H01L21/76897 ,  H01L29/66621

Abstract: A method for fabricating a semiconductor device includes forming at least two gate patterns on a substrate, forming sidewalls surrounding the gate patterns, wherein the sidewalls extend above an upper surface of the gate patterns, and forming a first conducting material in a first space and a second space, wherein the first space is provided above the gate patterns and between the sidewalls that extend above the upper surface of the gate patterns and the second space is provided between the gate patterns.

Abstract translation: 一种用于制造半导体器件的方法包括：在衬底上形成至少两个栅极图案，形成围绕所述栅极图案的侧壁，其中所述侧壁在所述栅极图案的上表面上方延伸，以及在第一空间中形成第一导电材料， 第二空间，其中第一空间设置在栅极图案上方以及在栅极图案的上表面之上延伸的侧壁之间，并且第二空间设置在栅极图案之间。