公开(公告)号：US20070042593A1

公开(公告)日：2007-02-22

申请号：US11553493

申请日：2006-10-27

Applicant: Jian-Hsing Lee ,  Pao-Kang Niu ,  Ko-Yi Lee

Inventor： Jian-Hsing Lee ,  Pao-Kang Niu ,  Ko-Yi Lee

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L23/60 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05138 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2224/45099

Abstract: A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edge portion, a second conductive layer having a wire bonding portion and a second edge portion and a plurality of plugs electrically connecting the wiring layer and the wire bonding portion. A conductive structure of an array of metal plugs or a metal damascene structure is formed to connect the first edge portion and the second edge portion, thereby preventing burn out of the first edge portion during an ESD event.

Abstract translation: 一种焊盘结构及其制造方法。 焊盘基本上由电介质层包围和绝缘，其中焊盘由具有带状布局的布线层和第一边缘部分的至少一个第一导电层形成，第二导电层具有引线接合部分， 第二边缘部分和电连接所述布线层和所述引线接合部分的多个插塞。 形成金属插塞或金属镶嵌结构阵列的导电结构以连接第一边缘部分和第二边缘部分，从而防止在ESD事件期间烧坏第一边缘部分。

公开(公告)号：US20060065931A1

公开(公告)日：2006-03-30

申请号：US10950844

申请日：2004-09-27

Applicant: Jian-Hsing Lee ,  Deng-Shun Chang

Inventor： Jian-Hsing Lee ,  Deng-Shun Chang

IPC: H01L23/62

CPC classification number: H01L27/0277 ,  H01L27/0255

Abstract: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.

公开(公告)号：US20060043491A1

公开(公告)日：2006-03-02

申请号：US11212000

申请日：2005-08-25

Applicant: Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

Inventor： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

IPC: H01L23/62

CPC classification number: H01L27/0255

Abstract: Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.

Abstract translation: 提供一种静电放电（ESD）保护装置及其制造方法。 在一个示例中，ESD保护装置包括形成在衬底中的齐纳二极管区域和邻近齐纳二极管区域形成的N型金属氧化物半导体（NMOS）器件。 齐纳二极管区域具有两个掺杂区域，位于两个掺杂区域之间的接地电位的栅极和在衬底中形成的两个光掺杂漏极（LDD）特征。 LDD特征之一位于两个掺杂区域和栅极之间。 NMOS器件包括形成在衬底中的源极和漏极，以及位于源极和漏极之间的第二栅极。

公开(公告)号：US06949802B2

公开(公告)日：2005-09-27

申请号：US10718363

申请日：2003-11-20

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee

IPC: H01L21/331 ,  H01L23/62 ,  H01L27/02 ,  H01L29/78 ,  H01L33/00

CPC classification number: H01L27/0255

Abstract: The invention describes structures and a process for providing ESD protection between multiple power supply lines or buses on an integrated circuit chip. Special diode strings are used for the protection devices whereby the diodes are constructed across the boundary of an N-well and P substrate or P-well. The unique design provides very low leakage characteristics during normal circuit operation, as well as improved trigger voltage control achieved by stacking 2 or more diodes in a series string between the power buses.

Abstract translation: 本发明描述了在集成电路芯片上的多个电源线或总线之间提供ESD保护的结构和过程。 专用二极管串用于保护装置，由此二极管跨越N阱和P衬底或P阱的边界构造。 独特的设计在正常电路操作期间提供非常低的泄漏特性，以及通过在电源总线之间串联串联的2个或更多个二极管来实现的改进的触发电压控制。

公开(公告)号：US20050082619A1

公开(公告)日：2005-04-21

申请号：US10687314

申请日：2003-10-16

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee ,  Tongchern Ong

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Tongchern Ong

IPC: H01L21/331 ,  H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H01L29/76

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a deep submicron electrostatic discharge (ESD) protection structure for a deep submicron integrated circuit (IC) and a method for forming such a structure. The structure includes at least two electrodes separated by a dielectric material, such as a thin gate oxide layer. In some examples, the thin gate oxide may be less than 25 Å thick. A source and drain are positioned proximate to and on opposite sides of one of the electrodes to form a channel. The drain is covered with a silicide layer that enhances the ESD protection provided by the structure. The source may also be covered with a silicide layer. In some examples, the drain may be floating.

Abstract translation: 本公开提供了用于深亚微米集成电路（IC）的深亚微米静电放电（ESD）保护结构以及用于形成这种结构的方法。 该结构包括由电介质材料隔开的至少两个电极，例如薄的栅极氧化物层。 在一些示例中，薄栅氧化物可以小于25埃。 源极和漏极位于电极之一附近和相对侧上以形成通道。 漏极覆盖有增强由结构提供的ESD保护的硅化物层。 源也可以用硅化物层覆盖。 在一些示例中，漏极可以是浮动的。

公开(公告)号：US06740934B2

公开(公告)日：2004-05-25

申请号：US10453008

申请日：2003-06-03

Applicant: Jian-Hsing Lee ,  Shui-Hun Chen ,  Jiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Shui-Hun Chen ,  Jiaw-Ren Shih

IPC: H01L2362

CPC classification number: H01L27/0266

Abstract: Disclosed are structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD) by preventing ESD current from flowing through resistive means between that output pad and an internal circuit. By splitting the active region and thereby creating a bipolar transistor which connects directly to the output pad, the resistive means is shunted when the bipolar transistor together with an already existing parasitic bipolar transistor conduct during ESD. Current flow in the resistive means is therefore eliminated and with it damaging power dissipation.

Abstract translation: 公开了通过防止ESD电流流过该输出焊盘和内部电路之间的电阻装置来增加静电放电（ESD）中的集成电路的输出焊盘功率消耗的结构和方法。 通过分离有源区，从而产生直接连接到输出焊盘的双极晶体管，当双极晶体管与已经存在的寄生双极晶体管在ESD期间导通时，电阻装置被分流。 因此，消除了电阻装置中的电流，并且损害了功率消耗。

公开(公告)号：US06614693B1

公开(公告)日：2003-09-02

申请号：US10100752

申请日：2002-03-19

Applicant: Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shui-Hung Chen ,  Jiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shui-Hung Chen ,  Jiaw-Ren Shih

IPC: G11C1604

CPC classification number: G11C16/3404 ,  G11C16/16

Abstract: A combination erase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. A first embodiment method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate, followed by a source erasing to further remove charges from the floating gate, and finally followed by a channel erasing to detrap charges. A second embodiment begins with a negative gate erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a source erasing to detrap the tunneling oxide of the EEPROM cell. A third embodiment begins with a source erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a channel erasing to detrap the tunneling oxide of the EEPROM cell.

Abstract translation: 从闪存EEPROM擦除数据的组合擦除方法消除了在快速EEPROM的隧道氧化物中捕获的电荷，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除快闪EEPROM单元的第一实施例方法是通过负栅极擦除开始，以从浮置栅极去除电荷，随后进行源擦除以进一步从浮置栅极去除电荷，最后再进行通道擦除以去除电荷。 第二实施例开始于负栅极擦除，其具有电压的增量步进以从浮置栅极去除电荷。 之后是源擦除来去除EEPROM单元的隧道氧化物。 第三实施例开始于具有逐渐增加的步进电压以从浮动栅极去除电荷的源擦除。 之后是通道擦除以去除EEPROM单元的隧穿氧化物。

公开(公告)号：US06610262B1

公开(公告)日：2003-08-26

申请号：US10086259

申请日：2002-03-04

Applicant: Kuo-Reay Peng ,  Jian-Hsing Lee

Inventor： Kuo-Reay Peng ,  Jian-Hsing Lee

IPC: H01L21336

CPC classification number: H01L27/0262 ,  H01L29/87

Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of a heavily doped P+ contact area residing in an N well region on a P substrate and electrically connected to the input pad of active integrated field effect transistor devices. NFET devices with floating gates and drains to reduce capacitance are located in the substrate near the N-well. The NFET source elements as well as the substrate are connected to ground. The NFETs are isolated from the N-well and associate P+ contact area by shallow trench isolation (STI) structures that reduce the NFET drain to substrate and N-well to substrate junction boundary area with a subsequent reduction in the junction capacitance. A voltage pulse from an ESD event will cause the SCR structure and associated parasitic bipolar transistors to trigger providing a path to ground for the ESD current, thereby protecting the internal circuits from damage.

Abstract translation: 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由驻留在P衬底上的N阱区中的重掺杂P +接触区域组成，并电连接到有源集成场效应晶体管器件的输入焊盘。 具有浮动栅极和漏极以降低电容的NFET器件位于靠近N阱的衬底中。 NFET源元件以及衬底连接到地。 NFET通过浅沟槽隔离（STI）结构与N阱隔离并且将P +接触区域相关联，从而将NFET漏极减少到衬底和N阱到衬底结边界区域，随后结电容的减小。 来自ESD事件的电压脉冲将导致SCR结构和相关联的寄生双极晶体管触发为ESD电流提供到地的路径，从而保护内部电路免受损坏。

公开(公告)号：US06552372B2

公开(公告)日：2003-04-22

申请号：US09827194

申请日：2001-04-05

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen ,  Jian-Ren Shih

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen ,  Jian-Ren Shih

IPC: H01L2972

CPC classification number: H01L27/0251

Abstract: An MOS integrated circuit, such as an input-output buffer, exhibits improved resistance to damage from electrostatic discharge (ESD) by balancing the ESD current flow through active and inactive sections of drivers. Better balance of the ESD current flow is achieved by increasing the width and length of nulti-finger channels of semiconductor material defining the gates of the drivers in the active section. Wider, longer gates of the drivers in the active section increase their ability to carry current, thereby resulting in a more symmetrical distribution of ESD current between the active and inactive sections without degrading the IC's normal performance.

Abstract translation: 诸如输入 - 输出缓冲器的MOS集成电路通过平衡通过驱动器的有源和非有效部分的ESD电流来改善对静电放电（ESD）的损坏。 通过增加限定有源部分中的驱动器的栅极的半导体材料的多指通道的宽度和长度来实现ESD电流的更好的平衡。 有源部分的驱动器较长的栅极增加了其承载电流的能力，从而导致有源和非活动部分之间的ESD电流分布更为对称，而不会降低IC的正常性能。

公开(公告)号：US06541824B2

公开(公告)日：2003-04-01

申请号：US09957275

申请日：2001-09-21

Applicant: Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Yi-Hsun Wu

Inventor： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Yi-Hsun Wu

IPC: H01L2362

CPC classification number: H01L27/0277 ,  H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors. When contacting an ESD voltage source to the collectors of the plurality of parasitic bipolar junction transistors, the junction formed between the collector and the base of the parasitic bipolar junction transistor enters into avalanche breakdown. The avalanche breakdown generates a large current through the substrate bulk resistances that is sufficiently large as to cause the base emitter junctions of all the parasitic bipolar junction transistors and turn on the parasitic bipolar junction transistors. The conduction of all the parasitic bipolar junction transistors is sufficient to cause the ESD voltage to be discharged thus preventing damage to the internal circuitry.