公开(公告)号：US20070257370A1

公开(公告)日：2007-11-08

申请号：US11733970

申请日：2007-04-11

Applicant: Jong-Cheol Lee ,  Kyoung-Ryul Yoon ,  Ki-Vin Im ,  Jae-Hyun Yeo ,  Eun-Ae Chung ,  Jin-Il Lee

Inventor： Jong-Cheol Lee ,  Kyoung-Ryul Yoon ,  Ki-Vin Im ,  Jae-Hyun Yeo ,  Eun-Ae Chung ,  Jin-Il Lee

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L21/44

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/75 ,  H01L28/90

Abstract: A multilayer electrode structure has a conductive layer including aluminum, an oxide layer formed on the conductive layer, and an oxygen diffusion barrier layer. The oxide layer includes zirconium oxide and/or titanium oxide. The oxygen diffusion barrier layer is formed at an interface between the conductive layer and the oxide layer by re-oxidizing the oxide layer. The oxygen diffusion barrier layer includes aluminum oxide.

Abstract translation: 多层电极结构具有包括铝的导电层，形成在导电层上的氧化物层和氧扩散阻挡层。 氧化物层包括氧化锆和/或氧化钛。 通过再氧化氧化层，在导电层和氧化物层之间的界面处形成氧扩散阻挡层。 氧扩散阻挡层包括氧化铝。

公开(公告)号：US20060244147A1

公开(公告)日：2006-11-02

申请号：US11339086

申请日：2006-01-25

Applicant: Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

Inventor： Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

IPC: H01L23/48

CPC classification number: H01L21/022 ,  H01L21/02142 ,  H01L21/02156 ,  H01L21/02175 ,  H01L21/28273 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/11502 ,  H01L27/11521

Abstract: In a method of manufacturing a dielectric structure, after a tunnel oxide layer pattern is formed on a substrate, a floating gate is formed on the tunnel oxide layer. After a first dielectric layer pattern including a metal silicon oxide and a second dielectric layer pattern including a metal silicon oxynitride are formed, a control gate is formed on the dielectric structure. Since the dielectric structure includes at least one metal silicon oxide layer and at least one metal silicon oxynitride layer, the dielectric structure may have a high dielectric constant and a good thermal resistance. A non-volatile semiconductor memory device including the dielectric structure may have good electrical characteristics such as a large capacitance and a low leakage current.

Abstract translation: 在制造电介质结构的方法中，在衬底上形成隧道氧化物层图案之后，在隧道氧化物层上形成浮栅。 在形成包括金属氧化硅和包括金属氮氧化硅的第二电介质层图案的第一电介质层图案之后，在电介质结构上形成控制栅极。 由于介电结构包括至少一个金属氧化硅层和至少一个金属氮氧化硅层，所以介电结构可以具有高介电常数和良好的耐热性。 包括电介质结构的非易失性半导体存储器件可能具有良好的电特性，例如大电容和低漏电流。

公开(公告)号：US20060216947A1

公开(公告)日：2006-09-28

申请号：US11376384

申请日：2006-03-15

Applicant: Jae-Hyoung Choi ,  Jung-hee Chung ,  Se-hoon Oh ,  Jong-cheol Lee

Inventor： Jae-Hyoung Choi ,  Jung-hee Chung ,  Se-hoon Oh ,  Jong-cheol Lee

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/0228 ,  C23C16/45529 ,  C23C16/45546 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L28/56

Abstract: Provided are methods of manufacturing dielectric films including forming a first dielectric film on a wafer using atomic layer deposition (ALD) in a first batch type apparatus, forming a second dielectric film on the first dielectric film using atomic layer deposition in a second batch type apparatus, wherein the second dielectric film has a higher crystallization temperature than the first dielectric film and forming a third dielectric film on the second dielectric film using atomic layer deposition in a third batch type apparatus. Methods of manufacturing metal-insulator-metal (MIM) capacitors using the methods of forming the dielectric films and batch type atomic layer deposition apparatus for forming the dielectric films are also provided.

Abstract translation: 提供了制造电介质膜的方法，包括在第一批式装置中使用原子层沉积（ALD）在晶片上形成第一电介质膜，在第二批式装置中使用原子层沉积在第一电介质膜上形成第二电介质膜 其中所述第二电介质膜具有比所述第一电介质膜更高的结晶温度，并且在第三批式装置中使用原子层沉积在所述第二电介质膜上形成第三电介质膜。 还提供了使用形成电介质膜的方法制造金属 - 绝缘体 - 金属（MIM）电容器的方法和用于形成电介质膜的分批型原子层沉积装置。

公开(公告)号：US20060063346A1

公开(公告)日：2006-03-23

申请号：US11149708

申请日：2005-06-10

Applicant: Jong-Cheol Lee ,  Ki-Vin Im ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Han-Mei Choi ,  Gab-Jin Nam

Inventor： Jong-Cheol Lee ,  Ki-Vin Im ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Han-Mei Choi ,  Gab-Jin Nam

IPC: H01L21/20

CPC classification number: H01L21/0228 ,  C23C16/45531 ,  C23C16/4554 ,  C23C16/45553 ,  C23C16/515 ,  H01L21/02274 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31691 ,  H01L28/40 ,  H01L28/65

Abstract: In a method of forming a layer using an atomic layer deposition process, after a substrate is loaded into a chamber, a reactant is provided onto the substrate to form a preliminary layer. Atoms in the preliminary layer are partially removed from the preliminary layer using plasma formed from an inert gas such as an argon gas, a xenon gas or a krypton gas, or an inactive gas such as an oxygen gas, a nitrogen gas or a nitrous oxide gas to form a desired layer. Processes for forming the desired layer may be simplified. A highly integrated semiconductor device having improved reliability may be economically manufactured so that time and costs required for the manufacturing of the semiconductor device may be reduced.

Abstract translation: 在使用原子层沉积工艺形成层的方法中，在将衬底装载到室中之后，将反应物提供到衬底上以形成预备层。 使用由诸如氩气，氙气或氪气等惰性气体形成的等离子体或氧气，氮气或一氧化二氮等惰性气体，从预备层中部分除去原料中的原子 气体形成所需层。 可以简化用于形成所需层的工艺。 可以经济地制造具有提高的可靠性的高度集成的半导体器件，从而可以减少制造半导体器件所需的时间和成本。

公开(公告)号：US20060044303A1

公开(公告)日：2006-03-02

申请号：US11148312

申请日：2005-06-09

Applicant: Seung-eon Lee ,  Kyoung-geun Lee ,  Jong-cheol Lee

Inventor： Seung-eon Lee ,  Kyoung-geun Lee ,  Jong-cheol Lee

IPC: G09G5/00

CPC classification number: H02M1/4208 ,  Y02B70/126

Abstract: A method of supplying a power to elements in a power supply apparatus including a primary side and a second side. Particularly, a method of supplying a driving power to an element at the primary side of the power supply apparatus from a primary coil of a transformer. A power factor improvement section improves a power factor of a received alternating current (AC) power. A transformer then receives the AC power having the improved power factor from a primary coil and generates an induced power at a secondary coil. The transformer then provides the AC power to drive a predetermined element located at the primary side of the power supply apparatus from the primary coil.

Abstract translation: 向包括初级侧和第二侧的电源装置中的元件供电的方法。 特别是一种从变压器的初级线圈向电源装置的初级侧的元件提供驱动电力的方法。 功率因数改善部分提高了接收的交流（AC）功率的功率因数。 然后，变压器从初级线圈接收具有改善的功率因数的AC电力，并在次级线圈处产生感应功率。 然后，变压器提供AC电力以从初级线圈驱动位于电源装置初级侧的预定元件。

公开(公告)号：US20050012498A1

公开(公告)日：2005-01-20

申请号：US10791629

申请日：2004-03-03

Applicant: Soo-Chan Lee ,  Young-Kyun Sun ,  Hyun-Ho Kim ,  Byeong-Chun Lee ,  Jun-Ho Lee ,  Jong-Cheol Lee ,  Je-Hyoung Ryu ,  Tae-Gyu Kim ,  Soon-Kyu Yim

Inventor： Soo-Chan Lee ,  Young-Kyun Sun ,  Hyun-Ho Kim ,  Byeong-Chun Lee ,  Jun-Ho Lee ,  Jong-Cheol Lee ,  Je-Hyoung Ryu ,  Tae-Gyu Kim ,  Soon-Kyu Yim

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  G01R31/02

CPC classification number: G01R31/2886 ,  G01R31/2893

Abstract: A semiconductor device test apparatus includes a main body and a stacker for stacking devices before and after a test. The stacker includes at least one user tray feeder predesignated with a function for stacking un-tested devices and at least one user tray sender predesignated with a function for stacking tested devices, the user tray functions being interchangeable during stacker operation.

Abstract translation: 半导体器件测试装置包括用于在测试之前和之后堆叠器件的主体和堆叠器。 所述堆垛机包括至少一个用户托盘进料器，所述用户托盘进料器具有用于堆叠未测试的装置的功能，并且至少一个用户托盘发送器预先具有用于堆叠测试的装置的功能，所述用户托盘功能在堆叠器操作期间是可互换的。

公开(公告)号：US06594818B2

公开(公告)日：2003-07-15

申请号：US09814565

申请日：2001-03-21

Applicant: Su-Chul Kim ,  Hyun-Geun Byun ,  Kwang-Jin Lee ,  Jong-Cheol Lee ,  Uk-Rae Cho

Inventor： Su-Chul Kim ,  Hyun-Geun Byun ,  Kwang-Jin Lee ,  Jong-Cheol Lee ,  Uk-Rae Cho

IPC: G06F1750

CPC classification number: H01L27/0207 ,  H01L21/82 ,  H01L27/10897

Abstract: A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced from different numbers of memory units on the generic wafer by forming one or more interconnect layer specialized according to a desired storage capacity and cutting the wafer using a sawing pattern according to the desired storage capacity. The specialized layer can be formed using different masks sets that form a different conductive pattern for each storage capacity or forming a generic interconnect structure with fuses that are cut to select the storage capacity of the memory chips

公开(公告)号：US06507224B1

公开(公告)日：2003-01-14

申请号：US10038171

申请日：2002-01-03

Applicant: Jong Cheol Lee ,  Yong Jin Yoon ,  Kwang Jin Lee

Inventor： Jong Cheol Lee ,  Yong Jin Yoon ,  Kwang Jin Lee

IPC: G11C2702

CPC classification number: H03K3/356139 ,  H03K3/012 ,  H03K3/356156

Abstract: An input receiver capable of sensing and amplifying an external signal having a very small swing input signal. The input receiver comprises a clock sampled amplifier for receiving a clock signal and a reference signal, respectively, in response to a first state of a clock signal and a delayed sampling clock signal, and for amplifying and sampling the voltage difference between the external signal and the reference signal, respectively, in response to a transition of the clock and delayed sampling clock signals to a second state; and a pulse generator for pre-charging a power source voltage and selectively pulling down the pre-charged signals to produce a pulse signal, in response to the second state of the delayed sampling clock signal and outputs of the clock sampled amplifier.

Abstract translation: 一种能够感测和放大具有非常小的摆动输入信号的外部信号的输入接收器。 输入接收机包括响应于时钟信号和延迟采样时钟信号的第一状态分别接收时钟信号和参考信号的时钟采样放大器，并且用于放大和采样外部信号与 分别响应于时钟的转变和延迟的采样时钟信号到第二状态的参考信号; 以及脉冲发生器，用于响应于延迟的采样时钟信号的第二状态和时钟采样放大器的输出，对电源电压进行预充电并选择性地拉低预充电信号以产生脉冲信号。

公开(公告)号：US5973201A

公开(公告)日：1999-10-26

申请号：US77976

申请日：1998-06-21

Applicant: No-Sang Park ,  Young-Sik Jung ,  Churl-Min Seong ,  Seung-Won Choi ,  Yeon-Joo Choi ,  Jong-Cheol Lee ,  Jin-Il Choi ,  Kwang-Sook Lee ,  Jae-Yang Kong ,  Bu-Yeon Lee ,  Jae-Hong Kim

Inventor： No-Sang Park ,  Young-Sik Jung ,  Churl-Min Seong ,  Seung-Won Choi ,  Yeon-Joo Choi ,  Jong-Cheol Lee ,  Jin-Il Choi ,  Kwang-Sook Lee ,  Jae-Yang Kong ,  Bu-Yeon Lee ,  Jae-Hong Kim

IPC: A61K31/165 ,  A61P25/04 ,  A61P29/00 ,  C07C235/18 ,  C07C235/34 ,  C07C323/20 ,  C07C323/25 ,  C07C323/41 ,  C07C233/00 ,  A01N43/30

CPC classification number: C07C235/34 ,  C07C323/41

Abstract: A phenylacetamide derivative of formula (I) have potent analgesic and anti-inflammatory activities and exhibit less irritability and toxicity: ##STR1## wherein, X, Y, W, n, m and Ar are as defined in the specification.

Abstract translation: PCT No.PCT / KR96 / 00239 Sec。 371日期：1998年6月12日 102（e）1998年6月12日PCT PCT 1996年12月11日PCT公布。 出版物WO97 / 21668 日期：1996年6月19日一种式（I）的苯乙酰胺衍生物具有强力的镇痛和抗炎活性，表现出较少的易怒和毒性：其中X，Y，W，n，m和Ar如说明书中所定义。