公开(公告)号：US20070236987A1

公开(公告)日：2007-10-11

申请号：US11727711

申请日：2007-03-28

Applicant: Woo-Yeong Cho ,  Kwang-Jin Lee ,  Hye-Jin Kim

Inventor： Woo-Yeong Cho ,  Kwang-Jin Lee ,  Hye-Jin Kim

IPC: G11C11/00

CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

Abstract translation: 相变存储器件通过接收在所选择的存储器单元中被编程的程序数据来执行编程操作，当检验读取电压为检测电压时，通过检测流过选择的存储器单元的检验电流的大小来感测已经存储在所选存储单元中的读取数据 应用于所选择的存储单元，确定读取的数据是否与程序数据相同，并且在确定所选择的存储单元中的一个或多个的程序数据与相应的读取数据不相同时，编程所选择的一个或多个 存储单元与程序数据。

公开(公告)号：US20070008769A1

公开(公告)日：2007-01-11

申请号：US11301322

申请日：2005-12-12

Applicant: Hye-Jin Kim ,  Du-Eung Kim ,  Kwang-Jin Lee ,  Yu-Hwan Ro

Inventor： Hye-Jin Kim ,  Du-Eung Kim ,  Kwang-Jin Lee ,  Yu-Hwan Ro

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Disclosed is a phase-changeable memory device and method of programming the same. The phase-changeable memory device includes memory cells each having multiple states, and a program pulse generator providing current pulses to the memory cells. The program pulse generator initializes a memory cell to a reset or set state by applying a first pulse thereto and thereafter provides a second pulse to program the memory cell to one of the multiple states. According to the invention, as a memory cell is programmed after being initialized to a reset or set state, it is possible to correctly program the memory cell without influence from the previous state of the memory cell.

Abstract translation: 公开了一种可变相存储器件及其编程方法。 相位可变存储器件包括各自具有多个状态的存储单元，以及向存储单元提供电流脉冲的编程脉冲发生器。 程序脉冲发生器通过向其施加第一个脉冲而将存储单元初始化为复位或置位状态，此后提供第二脉冲以将存储器单元编程为多个状态之一。 根据本发明，由于在初始化为复位或置位状态之后对存储单元进行编程，所以可以在不影响存储单元的先前状态的情况下正确编程存储单元。

公开(公告)号：US06933758B2

公开(公告)日：2005-08-23

申请号：US10308453

申请日：2002-12-03

Applicant: Tae-Hyoung Kim ,  Yong-Jin Yoon ,  Nam-Seog Kim ,  Kwang-Jin Lee

Inventor： Tae-Hyoung Kim ,  Yong-Jin Yoon ,  Nam-Seog Kim ,  Kwang-Jin Lee

IPC: G06F1/12 ,  G06F1/10 ,  H03K5/15 ,  H03L7/00 ,  H03L7/081 ,  H03L7/087

CPC classification number: H03L7/0814 ,  H03L7/087

Abstract: A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.

Abstract translation: 同步镜延迟电路包括用于延迟来自时钟缓冲电路的参考时钟信号的延迟监视电路。 正向延迟阵列顺序地延迟延迟监视电路的输出时钟信号以产生延迟时钟信号，并且镜像控制电路在延迟时钟信号中检测与参考时钟信号同步的延迟时钟信号。 后向延迟阵列延迟由镜像控制电路延迟的时钟信号，并且时钟驱动器接收反向延迟阵列的输出时钟信号以产生内部时钟信号。 当前向延迟阵列的延迟时钟信号与参考信号同步时，锁定范围控制电路控制传送到延迟监视器电路的每个时钟信号的延迟时间达到传送到时钟驱动器的每个信号的延迟时间量 时钟信号。

公开(公告)号：US06735674B2

公开(公告)日：2004-05-11

申请号：US09886308

申请日：2001-06-21

Applicant: Kwang-Jin Lee

Inventor： Kwang-Jin Lee

IPC: G06F1200

CPC classification number: G06F12/0846 ,  G06F13/1631

Abstract: A method and device for maintaining data coherency in a semiconductor memory device, having two or more memory chips combined into one chip and operated according to a late select synchronous pipeline type input/output protocol. A method includes the steps of generating first and second bypass summation signals by utilizing a chip block select address signal inputted in a latest write operation and comparison signals obtained from comparison between a latest write address and a current read address; and generating first and second bypass control signals having logic values contrary to each other by utilizing the first and second bypass summation signals and an internal clock signal, wherein a bypass operation is performed in one of read paths associated with the memory chips and a normal read operation is performed through other read paths when all the comparison signals are same.

Abstract translation: 一种用于在半导体存储器件中维持数据一致性的方法和装置，具有组合成一个芯片并根据后期选择同步流水线类型输入/输出协议进行操作的两个或多个存储器芯片。 一种方法包括以下步骤：通过利用在最新写入操作中输入的芯片块选择地址信号和从最新写入地址和当前读取地址之间的比较获得的比较信号来产生第一和第二旁路加和信号; 以及通过利用第一和第二旁路加法信号和内部时钟信号产生具有彼此相反的逻辑值的第一和第二旁路控制信号，其中在与存储器芯片相关联的读取路径和正常读取中执行旁路操作 当所有比较信号相同时，通过其它读取路径执行操作。

公开(公告)号：US06459637B1

公开(公告)日：2002-10-01

申请号：US09895196

申请日：2001-06-29

Applicant: Kwang-Jin Lee ,  Jong-Cheol Lee

Inventor： Kwang-Jin Lee ,  Jong-Cheol Lee

IPC: G11C700

CPC classification number: G11C29/02 ,  G11C7/06 ,  G11C7/1045 ,  G11C2207/2254

Abstract: An apparatus for controlling an enable of a sense amplifier in a semiconductor memory device includes a test part for repeatedly varying a test code value until the enable of the sense amplifier has a zero margin with respect to data to be read by the sense amplifier, and for determining the test code value at a time point when the enable has the zero margin. A fuse array cuts a fuse corresponding to the determined test code value.

Abstract translation: 一种用于控制半导体存储器件中的读出放大器的使能的装置包括用于重复地改变测试代码值的测试部件，直到读出放大器的使能相对于读出放大器要读取的数据为止为止，以及 用于在启用具有零余量的时间点确定测试代码值。 保险丝阵列切断与确定的测试代码值对应的保险丝。

公开(公告)号：US6166969A

公开(公告)日：2000-12-26

申请号：US345582

申请日：1999-06-30

Applicant: Byoung-Cheol Song ,  Hak-Soo Yu ,  Kwang-Jin Lee

Inventor： Byoung-Cheol Song ,  Hak-Soo Yu ,  Kwang-Jin Lee

IPC: G11C11/409 ,  G11C7/06 ,  G11C11/34 ,  H03K19/0185 ,  G11C7/00

CPC classification number: G11C7/06 ,  H03K19/018521

Abstract: Disclosed is a level shifter that can receive and convert a first signal that can have various voltage logic levels to a second signal having internal voltage logic levels. The level shifter includes first and second ascending/descending circuits, where the first ascend/descending circuit receives the first signal and the second ascend/descending circuit receives an inverted first signal. Each ascend/descending circuit is operable to descend a high logic level of the received signal to a low output voltage level and ascend a low logic level of the received signal to a high output voltage level. The output voltages from the first and second ascending/descending circuits are input to a sense amplifier that amplifies the difference between the output voltages in order to generate the internal voltage logic levels of the second signal. The first and second ascending/descending circuits buffer their respective received signals using the high logic level of the input signal as a supply voltage. The same principles are also applicable to the level shifting from internal voltage logic levels to external voltage logic levels.

Abstract translation: 公开了一种电平转换器，其可以接收和转换可以具有各种电压逻辑电平的第一信号到具有内部电压逻辑电平的第二信号。 电平移位器包括第一和第二上升/下降电路，其中第一上升/下降电路接收第一信号，第二上升/下降电路接收反相的第一信号。 每个上升/下降电路可操作以将接收信号的高逻辑电平降低到低输出电压电平，并将接收信号的低逻辑电平上升到高输出电压电平。 来自第一和第二上升/下降电路的输出电压被输入到放大输出电压之间的差的读出放大器，以产生第二信号的内部电压逻辑电平。 第一和第二上升/下降电路使用输入信号的高逻辑电平作为电源电压来缓冲它们各自的接收信号。 相同的原理也适用于从内部电压逻辑电平转换到外部电压逻辑电平的电平。

公开(公告)号：US09580361B2

公开(公告)日：2017-02-28

申请号：US14233424

申请日：2011-12-09

Applicant: Hyun Kuk Park ,  Ik Hyun Oh ,  Hee Jun Yoon ,  Hyeon Taek Son ,  Kwang Jin Lee ,  Hee Seon Bang ,  Han Sur Bang

Inventor： Hyun Kuk Park ,  Ik Hyun Oh ,  Hee Jun Yoon ,  Hyeon Taek Son ,  Kwang Jin Lee ,  Hee Seon Bang ,  Han Sur Bang

IPC: C04B35/64 ,  B22F3/105 ,  C04B35/56 ,  C04B35/645 ,  B23K20/12 ,  C22C29/08

CPC classification number: C04B35/64 ,  B22F3/105 ,  B23K20/1245 ,  C04B35/5626 ,  C04B35/645 ,  C04B2235/6562 ,  C04B2235/6581 ,  C04B2235/666 ,  C04B2235/77 ,  C04B2235/96 ,  C22C29/08

Abstract: The present invention relates to a preparation method of a tungsten carbide sintered body for a friction stir welding tool used in a friction stir welding tool of a high melting point material such as steel, titanium and the like or a dissimilar material such as aluminum, magnesium-steel, titanium and the like. The preparation method comprises the following steps: filling a tungsten carbide (WC) powder in a mold made of a graphite material; mounting the mold filled with tungsten carbide powder in a chamber of a discharge plasma sintering apparatus; making a vacuum inside of the chamber; molding the tungsten carbide powder while maintaining a constant pressure inside the mold and increasing the temperature according to a set heat increase pattern until the temperature reaches a final target temperature; and cooling the inside of the chamber while maintaining the pressure pressurized in the mold after the molding step.

Abstract translation: 本发明涉及一种用于摩擦搅拌焊接工具的碳化钨烧结体的制备方法，该工具用于诸如钢，钛等的高熔点材料的摩擦搅拌焊接工具或诸如铝，镁之类的异种材料 钛，钛等。 该制备方法包括以下步骤：在由石墨材料制成的模具中填充碳化钨（WC）粉末; 将填充有碳化钨粉末的模具安装在放电等离子体烧结装置的腔室中; 在室内进行真空; 在模具内保持恒定压力的同时成型碳化钨粉末，并根据设定的热量增加模式增加温度，直到温度达到最终目标温度; 并且在模制步骤之后保持在模具中加压的压力同时冷却腔室的内部。

公开(公告)号：US09034189B2

公开(公告)日：2015-05-19

申请号：US14114840

申请日：2012-06-21

Applicant: Jae Hee Ryu ,  Yong-Cheol Shin ,  Kwang-Jin Lee ,  Moo-Seok Lee

Inventor： Jae Hee Ryu ,  Yong-Cheol Shin ,  Kwang-Jin Lee ,  Moo-Seok Lee

IPC: B01D63/04 ,  B01D69/08 ,  B01D69/12 ,  B01D71/68 ,  B01D71/34 ,  B01D71/48 ,  B01D63/02 ,  B01D69/10

CPC classification number: B01D63/04 ,  B01D63/021 ,  B01D63/027 ,  B01D69/08 ,  B01D69/10 ,  B01D69/12 ,  B01D71/34 ,  B01D71/48 ,  B01D71/68 ,  B01D2313/23 ,  B01D2325/40

Abstract: Disclosed is a pressurized hollow fiber membrane module that exhibits improved durability without deterioration in packing density and permeation flux. The pressurized hollow fiber membrane module includes a composite hollow fiber membrane comprising a tubular braid woven by yarns and a polymer film on the outer surface of the tubular braid. At least one of the yarns comprises a small-fineness filament and a medium-fineness filament. The small-fineness filament comprises first monofilaments having a fineness of 0.01 to 0.4 denier, the medium-fineness filament comprises second monofilaments having a fineness higher than 0.4 and lower than 3, and a ratio of thickness of the tubular braid to outer diameter thereof is 15 to 35%.

Abstract translation: 公开了一种加压中空纤维膜组件，其具有改善的耐久性，而不会降低填充密度和渗透通量。 加压中空纤维膜组件包括复合中空纤维膜，其包括由纱线编织的管状编织物和在管状编织物的外表面上的聚合物膜。 至少一根纱线包括细细丝和中细丝。 小细丝包括细度为0.01至0.4旦尼尔的第一单丝，中细丝包括细度高于0.4且低于3的第二单丝，并且管状编织物的厚度与外径之比为 15到35％。

公开(公告)号：US20140073713A1

公开(公告)日：2014-03-13

申请号：US14115047

申请日：2012-08-14

Applicant: Yoon Ho Kim ,  Geon Soo Kim ,  Kwang Jin Lee

Inventor： Yoon Ho Kim ,  Geon Soo Kim ,  Kwang Jin Lee

IPC: C08L27/06 ,  C08L33/20

CPC classification number: C08L27/06 ,  C08J9/0061 ,  C08J2327/06 ,  C08J2425/14 ,  C08J2433/06 ,  C08L25/14 ,  C08L33/12 ,  C08L33/20 ,  C08L2205/02 ,  C08L2205/22 ,  C08L2312/00 ,  C08L51/003

Abstract: Disclosed is a crosslinked polymer nanoparticle containing composition, a method for preparing a copolymer using the composition, and a vinyl chloride resin with improved foam molding properties. Processing aid in according with the present invention, provides the effects of improved foam molding properties and processibility of a vinyl chloride resin, during a foam molding process upon being added to the vinyl chloride resin.

Abstract translation: 公开了一种含交联聚合物纳米颗粒的组合物，使用该组合物制备共聚物的方法和具有改进的发泡成型性能的氯乙烯树脂。 根据本发明的加工助剂在加入到氯乙烯树脂中的泡沫模制过程中提供改进的氯乙烯树脂的发泡成型性能和加工性的效果。

公开(公告)号：US08649204B2

公开(公告)日：2014-02-11

申请号：US13364942

申请日：2012-02-02

Applicant: Joon Min Park ,  Kwang Jin Lee

Inventor： Joon Min Park ,  Kwang Jin Lee

IPC: G11C11/00

CPC classification number: G11C29/1201 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/18

Abstract: A nonvolatile memory device includes an array of resistive memory cells and a write driver, which is configured to drive a selected bit line in the array with a reset current pulse, which is responsive to a first external voltage input through a first terminal/pad of the memory device during a memory cell reset operation. The write driver is further configured to drive the selected bit line in sequence with a first set current pulse, which is responsive to the first external voltage, and a second set current pulse, which is responsive to a second external voltage input through a second terminal/pad of the memory device during a memory cell set operation.

Abstract translation: 非易失性存储器件包括电阻存储器单元阵列和写驱动器，其被配置为以复位电流脉冲驱动阵列中的选定位线，该复位电流脉冲响应于通过第一端子/ 存储器单元重置操作期间的存储器件。 所述写入驱动器进一步被配置为按照响应于所述第一外部电压的第一设定电流脉冲和第二设定电流脉冲依次驱动所选位线，所述第二设定电流脉冲响应于通过第二端子输入的第二外部电压 /存储器单元设置操作的焊盘。