公开(公告)号：US10381394B2

公开(公告)日：2019-08-13

申请号：US15813414

申请日：2017-11-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Hotellier

IPC: H01L27/146 ,  H01L31/18 ,  H01L21/768

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

公开(公告)号：US20190229147A1

公开(公告)日：2019-07-25

申请号：US16251595

申请日：2019-01-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Yannick SANCHEZ ,  Emilie DELOFFRE

IPC: H01L27/146

Abstract: An image sensor manufacturing method includes forming a cavity in a first plate and mounting an active layer including both image sensing components and logic components to the first plate. The active layer is pressed against the first plate in a manner such that the image sensing components in the active layer are located on walls of the cavity and the logic components in the active layer are located outside of the cavity.

公开(公告)号：US10361238B2

公开(公告)日：2019-07-23

申请号：US15703246

申请日：2017-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

公开(公告)号：US10332808B2

公开(公告)日：2019-06-25

申请号：US15897003

申请日：2018-02-14

Applicant: Commissariat a l'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Stephan Niel ,  Emmanuel Richard ,  Olivier Weber

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/12 ,  H01L27/092

Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.

公开(公告)号：US10284798B2

公开(公告)日：2019-05-07

申请号：US15730539

申请日：2017-10-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Herault ,  Pierre Malinge

IPC: H04N5/365 ,  H04N5/353 ,  H04N5/374 ,  H04N5/355 ,  H04N5/3745 ,  H04N5/235

Abstract: An image sensor includes a plurality of pixels each including a first photodiode linked to a capacitive readout node by a first transistor, and a second photodiode linked to a first capacitive storage node by a second transistor, the first capacitive node being linked to the readout node by a third transistor, and the readout node being linked to a node for applying a reset potential by a fourth transistor.

公开(公告)号：US10283588B2

公开(公告)日：2019-05-07

申请号：US15845930

申请日：2017-12-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Perrin

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8238

Abstract: An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.

公开(公告)号：US10262898B2

公开(公告)日：2019-04-16

申请号：US15093416

申请日：2016-04-07

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Jean-Pierre Carrere ,  Jean-Luc Huguenin ,  Clement Pribat ,  Sarah Kuster

IPC: H01L21/768 ,  H01L21/82 ,  H01L27/12 ,  H01L29/70 ,  H01L27/082 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

公开(公告)号：US10256604B2

公开(公告)日：2019-04-09

申请号：US15739339

申请日：2015-06-26

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  UNIVERSITE PARIS DIDEROT

Inventor： Guillaume Crosnier ,  Fabrice Raineri ,  Rama Raj ,  Paul Monnier

IPC: H01S5/042 ,  H01S5/026 ,  H01S5/10 ,  H01S5/22 ,  H01S5/343 ,  B82Y20/00

Abstract: A semiconductor nanolaser includes a rib formed by a stack of layers, in which stack central layers (33, 34, 35) forming an assembly of quantum wells are placed between a lower layer (32) of a first conductivity type and an upper layer (36) of a second conductivity type. Holes (42) are drilled right through the thickness of the rib, wherein the lower layer includes first extensions (38, 40) that extend laterally on either side of the rib, and that are coated with first metallizations (42, 44) that are located a distance away from the rib. The stack includes second extensions (45, 46) that extend longitudinally beyond said rib, and that are coated with second metallizations (47, 48).

公开(公告)号：US20190067291A1

公开(公告)日：2019-02-28

申请号：US16111480

申请日：2018-08-24

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL ,  Quentin HUBERT ,  Thomas CABOUT

IPC: H01L27/108 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L27/10841 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10876 ,  H01L28/60 ,  H01L29/66181 ,  H01L29/945

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US10211059B2

公开(公告)日：2019-02-19

申请号：US15601115

申请日：2017-05-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Pierre Caubet ,  Florian Domengie ,  Carlos Augusto Suarez Segovia ,  Aurelie Bajolet ,  Onintza Ros Bengoechea

IPC: H01L29/49 ,  H01L21/28

Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.