公开(公告)号：US20040107230A1

公开(公告)日：2004-06-03

申请号：US10721655

申请日：2003-11-25

Applicant: STMicroelectronics S.A.

Inventor： Michel Bardouillet

IPC: G06F001/02

CPC classification number: G06F7/588 ,  H03K3/84

Abstract: A generator of random numbers by a flip-flop having a data input receiving a first signal at a first frequency comprised in a predetermined range and the instantaneous value of which is conditioned by a disturbing signal, and having a clock input receiving a second signal at a second predetermined frequency, smaller than the first one, said second signal passing through a delay element giving it a delay greater than or equal to the maximum period of the first signal.

Abstract translation: 一种由触发器产生的随机数的发生器，其具有数据输入，该数据输入以包含在预定范围内的第一频率接收第一信号，其瞬时值由干扰信号调节，并且具有接收第二信号的时钟输入 第二预定频率小于第一预定频率，所述第二信号通过延迟元件，给予其大于或等于第一信号的最大周期的延迟。

公开(公告)号：US20040101169A1

公开(公告)日：2004-05-27

申请号：US10717745

申请日：2003-11-20

Applicant: STMicroelectronics S.A.

Inventor： Christel-Loic Tisse ,  Laurent Plaza ,  Guillaume Petitjean

IPC: G06K009/00

CPC classification number: G06K9/00597

Abstract: A method and a system determine a score characteristic of the definition of a digital imageby cumulating the quadratic norm of horizontal and vertical gradients of luminance values of pixels of the image, the pixels being chosen at least according to a first maximum luminance threshold of other pixels in the concerned direction.

Abstract translation: 一种方法和系统通过累积图像的像素的亮度值的水平和垂直梯度的二次方程来确定数字图像的定义的分数特征，所述像素至少根据其他像素的第一最大亮度阈值来选择 在有关方向。

公开(公告)号：US20040073749A1

公开(公告)日：2004-04-15

申请号：US10270753

申请日：2002-10-15

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS, S.A.

Inventor： Sivagnanam Parthasarathy ,  Andrew Cofler ,  Lionel Chaverot

IPC: G06F012/00

CPC classification number: G06F9/381 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/3875 ,  G06F12/0864 ,  G06F12/0877 ,  G06F2212/1028 ,  Y02D10/13

Abstract: For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, where instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for any remaining iterations of the hardware loop to further reduce power consumption.

Abstract translation: 对于不会产生显着性能损失（如执行硬件循环）的指令集，处理器自动和动态切换到流水线的两周期访问关联的关联高速缓存而不是单周期访问。 涉及多个周期的访问使用更少的功率，因为​​只有高速缓存中的命中方式被访问，而不是索引的高速缓存行内的所有方式。 为了保持性能，在所有剩余指令中使用单周期高速缓存访​​问。 此外，在硬件环路内的指令集合完全适合预取缓冲器的情况下，高速缓存子系统对于硬件循环的任何剩余迭代都是空闲的，以进一步降低功耗。

公开(公告)号：US20040044943A1

公开(公告)日：2004-03-04

申请号：US10453844

申请日：2003-06-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Francois Jacquet ,  Jean-Pierre Schoellkopf

IPC: G11C029/00

CPC classification number: G06F11/1008 ,  G06F11/1048

Abstract: A memory circuit with an error correcting system comprising an address bus (102), an input data bus (108), and an output data bus (115), the circuit comprising a memory having an address bus (113), a data bus (114) and an error correcting circuit comprising an encoder (107). A first address register (104) is connected to the input address bus of the circuit for successively storing addresses corresponding to memory write operations only. A second data register (105) is connected to the input data bus of the circuit (108) for storing data transmitted to the encoder (107). Circuits make it possible to introduce a one-cycle shift into the memory writes, without modifying reads, giving the encoder more time to compute error correcting codes.

Abstract translation: 一种具有包括地址总线（102），输入数据总线（108）和输出数据总线（115）的纠错系统的存储器电路，该电路包括具有地址总线（113），数据总线 114）和包括编码器（107）的纠错电路。 第一地址寄存器（104）连接到电路的输入地址总线，用于仅依次存储对应于存储器写入操作的地址。 第二数据寄存器（105）连接到电路（108）的输入数据总线，用于存储发送到编码器（107）的数据。 电路使得可以在存储器写入中引入一个周期的移位，而不修改读取，给编码器更多的时间来计算纠错码。

公开(公告)号：US20040041600A1

公开(公告)日：2004-03-04

申请号：US10649711

申请日：2003-08-26

Applicant: STMICROELECTRONICS S.A.

Inventor： Lionel Grillo

IPC: H03B001/00

CPC classification number: H03L7/099 ,  H03B5/24 ,  H03B28/00 ,  H03L7/0891

Abstract: A sinusoidal frequency generator comprising an oscillation circuit controlled by a control voltage, characterized in that the oscillating circuit is a gyrator made up of two transconductance amplifiers whose bias points are fixed by the control voltage in order to regulate oscillation frequency. The gyrator is easy to integrated in a phase control loop in order to realize a square-to-sinusoidal frequency converter.

公开(公告)号：US20040033676A1

公开(公告)日：2004-02-19

申请号：US10421368

申请日：2003-04-23

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Coronel ,  Francois Leverd ,  Thomas Skotnicki

IPC: H01L021/20 ,  H01L021/36

CPC classification number: H01L21/6835 ,  H01L21/32134 ,  H01L21/76251 ,  H01L23/544 ,  H01L27/10852 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648 ,  H01L51/0013 ,  H01L2221/68363 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/83894 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints. In a preferred method, a selective treatment is applied to the transferred part of the initial structure, so as to make a distinction between the volumes of differentiated material of the pattern.

Abstract translation: 提供了一种用于制造集成电子部件的方法。 根据该方法，在第一基板的表面上产生初始结构。 该初始结构包含由差异化材料体积形成的限定图案。 包括限定图案的初始衬底的至少一部分被转移到第二衬底上，优选地通过使第一衬底相对于第二衬底反转，然后去除第一衬底。 然后在第二基板上产生另外的结构。 该附加结构包括与限定图案的一些体积不同的材料相对应放置的材料体积。 如此生产的电子部件可以根据技术或几何约束具有合适的构造。 在优选的方法中，对初始结构的转移部分应用选择性处理，以区分图案的差异材料的体积。

公开(公告)号：US20030218484A1

公开(公告)日：2003-11-27

申请号：US10405958

申请日：2003-04-02

Applicant: STMICROELECTRONICS S.A.

Inventor： Nicolas Graciannette ,  Benoit Marchand

IPC: H03L007/06

CPC classification number: G06F13/4217

Abstract: A device is provided for synchronizing, on a reference clock signal, an exchange of data with a remote member. The device includes a main variable delay line controlled by a first processing unit coupled to a phase comparator in order to generate a delayed clock signal transmitted to the remote member. One input of the main variable delay line receives the reference clock signal. The device also includes a first terminal for receiving a clock signal image received by the remote member, a first auxiliary variable delay line having one input connected to the first terminal and one output connected to a first input of the phase comparator, a second auxiliary variable delay line having one input connected to the input of the main variable delay line and one output connected to a second input of the phase comparator, and a second processing unit controlling the first and second auxiliary variable delay lines so that the signal image received by the remote member is offset with respect to the reference clock signal, by a phase suitable for synchronizing the exchange of data on the reference clock signal.

Abstract translation: 提供了一种设备，用于在参考时钟信号上与远程成员进行数据交换。 该装置包括由连接到相位比较器的第一处理单元控制的主可变延迟线，以便产生发送给远程成员的延迟时钟信号。 主可变延迟线的一个输入端接收参考时钟信号。 该装置还包括用于接收由远程成员接收的时钟信号图像的第一终端，具有连接到第一终端的一个输入和连接到相位比较器的第一输入的一个输出的第一辅助可变延迟线，第二辅助变量 延迟线，其一个输入连接到主可变延迟线的输入，一个输出连接到相位比较器的第二输入，第二处理单元控制第一和第二辅助可变延迟线，使得由 远程成员相对于参考时钟信号偏移适合于同步参考时钟信号上的数据交换的相位。

公开(公告)号：US20030137351A1

公开(公告)日：2003-07-24

申请号：US10319425

申请日：2002-12-12

Applicant: STMicroelectronics S.A.

Inventor： Claude Renous ,  Kuno Lenz

IPC: H03F003/45

CPC classification number: H03F3/45475 ,  H03F1/086 ,  H03F2200/372 ,  H03F2203/45008 ,  H03F2203/45082

Abstract: A low noise differential amplifier structure comprising a first amplifier provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. A second amplifier is provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. The structure is characterized in that it comprises: at least a first trimming capacitor having a first electrode connected to the first electrode of the first Miller capacitor; at least a second trimming capacitor having a first electrode connected to the first electrode of the second Miller capacitor; and a cascode stage having an input receiving the output common mode voltage and an output connected to the second electrode of the first and second trimming capacitors.

Abstract translation: 一种低噪声差分放大器结构，包括具有输出级的第一放大器，分别具有与输出级的输入端和输出端连接的第一电极和第二电极的米勒电容器。 第二放大器设置有输出级，其具有分别连接到输出级的输入端和输出端的第一电极和第二电极的米勒电容器。 该结构的特征在于它包括：至少第一微调电容器，其具有连接到第一米勒电容器的第一电极的第一电极; 至少第二微调电容器，其具有连接到第二米勒电容器的第一电极的第一电极; 以及级联级，其具有接收输出共模电压的输入端和连接到第一和第二微调电容器的第二电极的输出端。

公开(公告)号：US20030122249A1

公开(公告)日：2003-07-03

申请号：US10298189

申请日：2002-11-14

Applicant: STMICROELECTRONICS S.A.

Inventor： Christophe Prior

IPC: H01L023/32

CPC classification number: H01L27/14618 ,  H01L24/32 ,  H01L24/83 ,  H01L31/0203 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/12043 ,  H01L2924/16195 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package is provided that includes an electrical connection and support means having a front face and a recess in the front face. The semiconductor package also includes a semiconductor component having a front face including a sensor and a rear face which presses on the bottom of the recess of the electrical connection and support means. Further included in the semiconductor package is a positioning and locking means for locking the semiconductor component onto the electrical connection and support means. The positioning and locking means is engaged in a space which separates the periphery of the semiconductor component from the periphery of the recess and keeps the semiconductor component pressed against the bottom of the recess. Thus, there is provided a semiconductor package having efficiently oriented components.

Abstract translation: 提供一种半导体封装，其包括电连接和支撑装置，其具有正面和前表面中的凹部。 半导体封装还包括半导体部件，其具有包括传感器的前表面和压在电连接和支撑装置的凹部的底部上的后表面。 还包括在半导体封装中的是用于将半导体部件锁定到电连接和支撑装置上的定位和锁定装置。 定位和锁定装置接合在将半导体部件的周边与凹部的周边分开的空间中，并使半导体部件压靠在凹部的底部。 因此，提供了具有有效取向的部件的半导体封装。

公开(公告)号：US20030095209A1

公开(公告)日：2003-05-22

申请号：US10299160

申请日：2002-11-18

Applicant: STMICROELECTRONICS S.A.

Inventor： Francois Van Zanten ,  Marc Sabut ,  Raymond Ribas

IPC: H04N005/14

CPC classification number: H04N5/18

Abstract: An input stage for a video receiver includes a variable gain amplifier, an analog-to-digital converter for sampling a video signal and a digital processing unit for processing digital samples of the video signal. An analog regulating circuit sets an input potential at an input of the variable gain amplifier. A differential architecture is used for the variable gain amplifier and the digital analog converter. A conversion circuit between an input coupling capacitor and the variable gain amplifier allows generating the video signal on two channels in antiphase, which are centered on the common mode voltage. Such differential architecture allows reducing the amplitude of analog signals, which is particularly advantageous in the case of a low voltage supply delivering a few volts. In addition, linearity of the video signal processing is enhanced.

Abstract translation: 用于视频接收机的输入级包括可变增益放大器，用于对视频信号进行采样的模数转换器和用于处理视频信号的数字采样的数字处理单元。 模拟调节电路在可变增益放大器的输入端设置输入电位。 差分架构用于可变增益放大器和数字模拟转换器。 输入耦合电容器和可变增益放大器之间的转换电路允许在以共模为中心的反相中的两个通道上产生视频信号。 这种差分架构允许降低模拟信号的幅度，这在低电压电源传送几伏的情况下是特别有利的。 此外，增强了视频信号处理的线性度。