公开(公告)号：US20070040227A1

公开(公告)日：2007-02-22

申请号：US11586791

申请日：2006-10-26

申请人： Suman Datta ,  Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

发明人： Suman Datta ,  Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

IPC分类号： H01L29/94

CPC分类号： H01L29/4983 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606

摘要： In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have vertical portions that may be exposed to a reduction reaction. As a result of the reduction reaction, the vertical portions may be converted to metal, which adds to the existing gate electrode. In some cases, removing the vertical dielectric portions reduces fringe capacitance and may also advantageously slightly increased underdiffusion without adding heat, in some embodiments.

摘要翻译： 在金属栅极更换工艺中，杯状栅极金属氧化物电介质可以具有可能暴露于还原反应的垂直部分。 作为还原反应的结果，垂直部分可以转化为金属，这增加了现有的栅电极。 在一些实施例中，在一些实施例中，去除垂直电介质部分减少了边缘电容，并且还可以有利地稍微增加向下扩散而不加热。

公开(公告)号：US20060286729A1

公开(公告)日：2006-12-21

申请号：US11159430

申请日：2005-06-21

申请人： Jack Kavalieros ,  Annalisa Cappellani ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Chris Barns ,  Robert Chau

发明人： Jack Kavalieros ,  Annalisa Cappellani ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Chris Barns ,  Robert Chau

IPC分类号： H01L21/338

CPC分类号： H01L29/66636 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7834

摘要： A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the-removal of a nitride etch stop layer.

公开(公告)号：US20060278941A1

公开(公告)日：2006-12-14

申请号：US11151528

申请日：2005-06-13

申请人： Matthew Metz ,  Suman Datta ,  Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Robert Chau

发明人： Matthew Metz ,  Suman Datta ,  Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Robert Chau

IPC分类号： H01L29/94

CPC分类号： H01L21/31691 ,  H01L21/02197 ,  H01L21/02269 ,  H01L21/02293 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/517

摘要： A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.

公开(公告)号：US20060205167A1

公开(公告)日：2006-09-14

申请号：US11078267

申请日：2005-03-11

申请人： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Brian Doyle ,  Robert Chau ,  Everett Wang ,  Philippe Matagne ,  Lucian Shifren ,  Been Jin ,  Mark Stettler ,  Martin Giles

发明人： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Brian Doyle ,  Robert Chau ,  Everett Wang ,  Philippe Matagne ,  Lucian Shifren ,  Been Jin ,  Mark Stettler ,  Martin Giles

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/8234

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  Y10S438/933

摘要： A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

摘要翻译： 晶体管可以由不同层的硅锗形成，具有梯度锗浓度的最低层和具有恒定锗浓度的上层，使得最底层具有Si 1-x Ge Ge > x 。 在PMOS侧，最高层可以是Si 1-y N y O y的形式。 源极和漏极可以由PMOS侧的Si 1-z N z z z的外延硅锗形成。 在一些实施例中，在PMOS器件中，x大于y且z大于x。 因此，PMOS器件可以在通道方向上具有单轴压应力和面内双轴压应力。 在某些情况下，应力的这种组合可能导致较高的移动性和增加的设备性能。

公开(公告)号：US20060148182A1

公开(公告)日：2006-07-06

申请号：US11028378

申请日：2005-01-03

申请人： Suman Datta ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Mark Doczy ,  Robert Chau

发明人： Suman Datta ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Mark Doczy ,  Robert Chau

IPC分类号： H01L21/336

CPC分类号： H01L29/66871 ,  H01L29/7784

摘要： A quantum well transistor or high electron mobility transistor may be formed using a replacement metal gate process. A dummy gate electrode may be used to define sidewall spacers and source drain contact metallizations. The dummy gate electrode may be removed and the remaining structure used as a mask to etch a doped layer to form sources and drains self-aligned to said opening. A high dielectric constant material may coat the sides of said opening and then a metal gate electrode may be deposited. As a result, the sources and drains are self-aligned to the metal gate electrode. In addition, the metal gate electrode is isolated from an underlying barrier layer by the high dielectric constant material.

摘要翻译： 可以使用替代金属栅极工艺形成量子阱晶体管或高电子迁移率晶体管。 可以使用虚拟栅电极来限定侧壁间隔件和源漏接触金属化。 可以去除虚拟栅电极，并且将剩余的结构用作掩模以蚀刻掺杂层以形成源并且将其排列到所述开口自对准。 高介电常数材料可以覆盖所述开口的侧面，然后可以沉积金属栅极电极。 结果，源极和漏极与金属栅电极自对准。 此外，金属栅电极通过高介电常数材料与下面的阻挡层隔离。

公开(公告)号：US20060121727A1

公开(公告)日：2006-06-08

申请号：US11006074

申请日：2004-12-07

申请人： Matthew Metz ,  Suman Datta ,  Mark Doczy ,  Jack Kavalieros ,  Justin Brask ,  Robert Chau

发明人： Matthew Metz ,  Suman Datta ,  Mark Doczy ,  Jack Kavalieros ,  Justin Brask ,  Robert Chau

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966

摘要： A method for making a titanium carbide layer is described. That method comprises alternately introducing a carbon containing precursor and a titanium containing precursor into a chemical vapor deposition reactor, while a substrate is maintained at a selected temperature. The reactor is operated for a sufficient time, and pulse times are selected for the carbon containing precursor and the titanium containing precursor, to form a titanium carbide layer of a desired thickness and workfunction on the substrate.

摘要翻译： 对碳化钛层的制造方法进行说明。 该方法包括在将基底保持在选定温度的同时将含碳前体和含钛前体交替引入化学气相沉积反应器。 反应器运行足够的时间，并且对于含碳的前体和含钛的前体选择脉冲时间，以在基底上形成所需厚度和功函数的碳化钛层。

公开(公告)号：US20060051880A1

公开(公告)日：2006-03-09

申请号：US10935784

申请日：2004-09-07

申请人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

发明人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

摘要： A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

公开(公告)号：US20060022277A1

公开(公告)日：2006-02-02

申请号：US10900582

申请日：2004-07-28

申请人： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Uday Shah ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau

发明人： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Uday Shah ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7843

摘要： A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop.

公开(公告)号：US20060003499A1

公开(公告)日：2006-01-05

申请号：US10882733

申请日：2004-06-30

申请人： Mark Doczy ,  Robert Norman ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Suman Datta ,  Robert Chau

发明人： Mark Doczy ,  Robert Norman ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Suman Datta ,  Robert Chau

IPC分类号： H01L21/335 ,  H01L21/425 ,  H01L21/44

CPC分类号： H01L21/28176 ,  H01L21/3105 ,  H01L21/31111 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517

摘要： A metal oxide layer on a substrate is converted at least partly to a metal layer. At least part of the metal layer is covered by an oxidation resistant cover. The covered layer and underlying metal may be removed, for example, using acid.

公开(公告)号：US20060001106A1

公开(公告)日：2006-01-05

申请号：US10881055

申请日：2004-06-30

申请人： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

发明人： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/823828 ,  H01L21/823857

摘要： Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a replacement process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.

摘要翻译： 互补金属氧化物半导体集成电路可以由具有不同栅极电介质的NMOS和PMOS晶体管形成。 可以例如通过替换处理形成不同的栅极电介质。 作为几个示例，栅极电介质可能在材料，厚度或形成技术上不同。