公开(公告)号：US10804398B2

公开(公告)日：2020-10-13

申请号：US16160701

申请日：2018-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66

Abstract: A device including source-drain epitaxy contacts with a trench silicide (TS) liner wrapped around the source-drain contacts, and method of production thereof. Embodiments include a device having a gate structure formed over a substrate; source-drain epitaxy contacts including a trench silicide (TS) liner covering the source-drain epitaxy contacts; TS contacts formed on the TS liner over the source-drain epitaxy contacts; and a dielectric pillar disposed in a TS cut between the source-drain epitaxy contacts. The TS liner wraps around the source-drain epitaxy contacts, including bottom negatively tapered surfaces of the source-drain epitaxy contacts.

公开(公告)号：US20200286900A1

公开(公告)日：2020-09-10

申请号：US16295485

申请日：2019-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy W. Mann ,  Bipul C. Paul ,  Julien Frougier ,  Ruilong Xie

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

Abstract: Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

公开(公告)号：US10763342B2

公开(公告)日：2020-09-01

申请号：US16216356

申请日：2018-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234

Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.

公开(公告)号：US10734525B2

公开(公告)日：2020-08-04

申请号：US15920886

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Christopher M. Prindle ,  Nigel G. Cave

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

Abstract: The disclosure relates to gate-all-around (GAA) transistors with a spacer support, and related methods. A GAA transistor according to embodiments of the disclosure includes: at least one semiconductor channel structure extending between a source terminal and a drain terminal; a spacer support having a first portion thereof positioned underneath and a second portion thereof positioned alongside a first portion of the at least one semiconductor channel structure; and a gate metal surrounding a second portion of the at least one semiconductor channel structure between the source and drain terminals; wherein the spacer support is positioned between the gate metal and the source or drain terminal.

公开(公告)号：US10707206B2

公开(公告)日：2020-07-07

申请号：US16194691

申请日：2018-11-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L27/08 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311

Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.

公开(公告)号：US10699942B2

公开(公告)日：2020-06-30

申请号：US15961337

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/78

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

公开(公告)号：US20200168731A1

公开(公告)日：2020-05-28

申请号：US16776807

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/768 ,  H01L29/08

Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.

公开(公告)号：US20200168504A1

公开(公告)日：2020-05-28

申请号：US16778884

申请日：2020-01-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal Kamineni ,  Ruilong Xie ,  Mark Raymond

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/417

Abstract: Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.

公开(公告)号：US10665586B2

公开(公告)日：2020-05-26

申请号：US15708911

申请日：2017-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Cheng Chi

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L29/08 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/285 ,  H01L21/8234 ,  H01L21/311

Abstract: A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.

公开(公告)号：US20200161296A1

公开(公告)日：2020-05-21

申请号：US16194691

申请日：2018-11-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.