公开(公告)号：US07267350B2

公开(公告)日：2007-09-11

申请号：US10853847

申请日：2004-05-25

申请人： Shinichi Yamada ,  Takeshi Wakabayashi ,  Takehiko Nanri ,  Kiyotaka Sakai

发明人： Shinichi Yamada ,  Takeshi Wakabayashi ,  Takehiko Nanri ,  Kiyotaka Sakai

IPC分类号： B62K21/08

CPC分类号： F16F9/145 ,  B62K21/08

摘要： A steering damper includes a steering damper body installed in a steering system of a vehicle, and having a fluid path therein, and a pressure control valve for controlling a damping force in the steering system, and provided in the fluid path, wherein the pressure control valve controls the damping force so that an increasing rate of the damping force with respect to a steering angular velocity when the steering angular velocity is large is lower than that when the steering angular velocity is small.

摘要翻译： 转向阻尼器包括安装在车辆的转向系统中并具有流体路径的转向阻尼器主体和用于控制转向系统中的阻尼力并设置在流体路径中的压力控制阀，其中压力控制 阀控制阻尼力，使得当转向角速度大时相对于转向角速度的阻尼力的增加速率低于转向角速度较小时的减速力的增加率。

公开(公告)号：US07145825B2

公开(公告)日：2006-12-05

申请号：US10800831

申请日：2004-03-16

申请人： Kaoru Mori ,  Katuhiro Mori ,  Shinichi Yamada ,  Kuninori Kawabata ,  Shigemasa Ito

发明人： Kaoru Mori ,  Katuhiro Mori ,  Shinichi Yamada ,  Kuninori Kawabata ,  Shigemasa Ito

IPC分类号： G11C7/00

CPC分类号： G11C11/406

摘要： A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.

摘要翻译： 一种在移位寄存器的驱动控制信号中具有低功耗的半导体存储器件。 该装置包含多个存储单元阵列，每个存储单元阵列由预定数量的存储单元行组成。 一组移位寄存器耦合到每个单元阵列，并且第n组移位寄存器根据给定的控制信号依次激活字线选择信号，使得第n个单元阵列的相应字线将被刷新。 还耦合到每个单元阵列是移位寄存器控制器。 当第n个单元阵列被刷新时，第n个移位寄存器控制器向第n组移位寄存器提供控制信号。 当完成该单元阵列的刷新时，第n移位寄存器控制器将控制信号转发到第（n + 1）个移位寄存器组，从而启动第（n + 1）个单元阵列的刷新操作。

公开(公告)号：US20060098523A1

公开(公告)日：2006-05-11

申请号：US11313963

申请日：2005-12-22

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C8/00

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

公开(公告)号：US07021433B2

公开(公告)日：2006-04-04

申请号：US10796572

申请日：2004-03-09

申请人： Shinichi Yamada ,  Kiyotaka Sakai ,  Takehiko Nanri ,  Takeshi Wakabayashi

发明人： Shinichi Yamada ,  Kiyotaka Sakai ,  Takehiko Nanri ,  Takeshi Wakabayashi

IPC分类号： F16D57/02 ,  F16F9/14

CPC分类号： F16F9/145 ,  B62K21/08

摘要： A steering damper in a motorcycle includes a vane partitioning a chamber in a damper housing into two oil chambers, wherein hydraulic fluid flows between the two chambers to generate attenuating force. The steering damper also includes a damper shaft connected to the vane and supporting the vane for rocking motion with respect to the housing, and a hydraulic pressure control valve. The housing is attached to a head pipe, and the damper shaft is attached to a steering system. When the head pipe is to be attached to the housing, the housing is extended rearwardly behind a top bridge, and a linear solenoid for driving and controlling the hydraulic pressure control valve is attached to the housing and disposed below the extension thereof.

摘要翻译： 摩托车中的转向阻尼器包括将阻尼器壳体中的室分隔成两个油室的叶片，其中液压流体在两个室之间流动以产生衰减力。 转向阻尼器还包括连接到叶片并且支撑叶片以相对于壳体摇摆运动的阻尼器轴和液压控制阀。 壳体附接到头管，并且阻尼器轴附接到转向系统。 当头管要附接到壳体时，壳体在顶桥后方向后延伸，并且用于驱动和控制液压控制阀的线性螺线管被附接到壳体并设置在其延伸部的下方。

公开(公告)号：US20050265116A1

公开(公告)日：2005-12-01

申请号：US10994632

申请日：2004-11-23

申请人： Kota Hara ,  Shinichi Yamada

发明人： Kota Hara ,  Shinichi Yamada

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C7/20 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/4072

摘要： A semiconductor memory device, in which a burst operation is performed using a memory core, has a read/write trigger signal generating circuit and a read/write signal generating circuit. The read/write trigger signal generating circuit generates a read/write signal request from a predetermined timing signal during the burst operation. The read/write signal generating circuit receives an output signal from the read/write trigger signal generating circuit and outputs a read/write signal after a core operation just prior to receipt of the output signal is complete and the subsequent activation of a row side is complete.

摘要翻译： 使用存储器核进行突发操作的半导体存储器件具有读/写触发信号生成电路和读/写信号生成电路。 读/写触发信号产生电路在脉冲串操作期间从预定定时信号产生读/写信号请求。 读/写信号发生电路在读/写触发信号产生电路接收输出信号，并且在接收到输出信号完成之后在核心操作之后输出读/写信号，并且随后的行侧激活 完成。

公开(公告)号：US20050094480A1

公开(公告)日：2005-05-05

申请号：US11001619

申请日：2004-12-02

申请人： Shinya Fujioka ,  Shinichi Yamada ,  Kotoku Sato ,  Jun Ohno

发明人： Shinya Fujioka ,  Shinichi Yamada ,  Kotoku Sato ,  Jun Ohno

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4193 ,  G11C8/02

CPC分类号： G11C7/1018 ,  G11C7/22 ,  G11C2207/2227

摘要： A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

摘要翻译： 一种用于控制可以以突发模式设置模式寄存器的半导体存储器的方法。 为了在突发模式下设置操作模式，首先将半导体存储器从突发模式（通过掉电模式）改变为非突发模式的待机模式。 然后，当以与非突发模式中使用的相同的预定顺序输入命令时，半导体存储器被改变为模式寄存器设置模式以设置模式寄存器。

公开(公告)号：US06868023B2

公开(公告)日：2005-03-15

申请号：US10656374

申请日：2003-09-08

申请人： Masato Takita ,  Shinichi Yamada ,  Masato Matsumiya

发明人： Masato Takita ,  Shinichi Yamada ,  Masato Matsumiya

IPC分类号： G11C11/403 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4099 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C7/062 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4099

摘要： A semiconductor memory device includes a plurality of bit line pairs, each of which includes a first bit line and a second bit line, a plurality of memory cells which are coupled to said first bit line, and store electric charge in capacitors, a dummy cell which is coupled to a second bit line, and is charged with a predetermined potential, a sense amplifier which amplifies a potential difference between the first bit line and the second bit line, and a control circuit which charges said dummy cell with the predetermined potential only for a fixed time period.

摘要翻译： 半导体存储器件包括多个位线对，每个位线对包括第一位线和第二位线，耦合到所述第一位线的多个存储器单元，并将电荷存储在电容器中;虚拟单元 其被耦合到第二位线，并且被充电为预定电位;放大器，用于放大第一位线和第二位线之间的电位差;以及控制电路，其对所述虚设单元充电仅具有预定电位 固定时间段。

公开(公告)号：US20050010526A1

公开(公告)日：2005-01-13

申请号：US10915566

申请日：2004-08-11

申请人： Naoki Takahashi ,  Hiromitsu Shiina ,  Masahito Matsunawa ,  Shinichi Yamada ,  Yoshiharu Kamada ,  Tsuyoshi Miyake ,  Akira Okamura ,  Masasuke Tominaga

发明人： Naoki Takahashi ,  Hiromitsu Shiina ,  Masahito Matsunawa ,  Shinichi Yamada ,  Yoshiharu Kamada ,  Tsuyoshi Miyake ,  Akira Okamura ,  Masasuke Tominaga

IPC分类号： G06Q20/00 ,  G06F17/60

CPC分类号： G06Q20/02 ,  G06Q10/087 ,  G06Q20/00 ,  G06Q20/10 ,  G06Q20/102 ,  G06Q20/389 ,  G06Q20/40 ,  G06Q30/0601 ,  G06Q30/0615 ,  G06Q40/12 ,  G06Q50/188 ,  G07F11/002

摘要： A center site is disposed to intervene in a business transaction achieved through a network. The center site includes an open business information database in which open business information received from member sites connected to the network is accumulated to be opened to the sites and a notarization database to keep therein contents of contracts of transactions between the sites. The center site receives a transaction request from a transaction partner site in accordance with the open business information and notifies the request to an information supply site associated therewith. The center site intervenes in a transaction resultantly accomplished between the information supply site and the transaction partner site and conducts a notarization process for the contents of contract for the transaction to accumulate the contract in a notarization database.

摘要翻译： 处理一个中心站点介入通过网络实现的业务交易。 该中心站点包括一个开放的业务信息数据库，其中从网络连接的成员站点收到的开放业务信息被累积到该站点，以及一个公证数据库，以便在站点之间保留交易合同的内容。 中心站点根据开放的业务信息从交易伙伴站点接收交易请求，并将该请求通知给与其相关联的信息提供站点。 中心站点介入信息提供站点和交易对象站点之间完成的交易，对交易合同内容进行公证程序，在公证数据库中累积合同。

公开(公告)号：US06834021B2

公开(公告)日：2004-12-21

申请号：US10350191

申请日：2003-01-24

申请人： Kaoru Mori ,  Shinichi Yamada

发明人： Kaoru Mori ,  Shinichi Yamada

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： An operation control circuit sets an inactivating timing of sense amplifiers activated in response to a read request, a write request, or a refresh request, to the timing a maximum possible quantity of signals which can be output from the sense amplifiers operating in response to the refresh request is transmitted to memory cells. Tailoring the activating period of the sense amplifiers to a refresh operation can reduce access time. A refresh control circuit generates a predetermined number of refresh requests consecutively to refresh all of the memory cells before extending the cycle of generating refresh requests. When refresh requests occur consecutively, the refresh frequency can be lowered to reduce power consumption. As a result, access time can be reduced without increasing power consumption during the standby mode.

摘要翻译： 操作控制电路将响应于读取请求，写入请求或刷新请求而被激活的读出放大器的失活定时设置为能够响应于所述读取放大器操作的读出放大器输出的最大可能量的信号的定时 刷新请求被传送到存储单元。 将感测放大器的激活周期调整到刷新操作可以减少访问时间。 刷新控制电路在扩展生成刷新请求的周期之前，连续生成预定数量的刷新请求以刷新所有存储单元。 当刷新请求连续发生时，可以降低刷新频率以降低功耗。 结果，可以在待机模式期间不增加功耗来降低访问时间。

公开(公告)号：US06278647B1

公开(公告)日：2001-08-21

申请号：US09537385

申请日：2000-03-29

申请人： Satoru Saitoh ,  Shinichi Yamada ,  Masato Takita

发明人： Satoru Saitoh ,  Shinichi Yamada ,  Masato Takita

IPC分类号： G11C800

CPC分类号： G11C7/1006 ,  G11C7/10 ,  G11C8/12

摘要： Connections of global data buses GDB0 and GDB1 to local data buses LDB00 to LDB04 in a bank 1 are reverse to those in a bank 0. That is, the global data bus GDB0 is connected to every other local data bus LDB00, LDB02 and LDB04 including both sides in the bank 0, and to every other local data buses LDB11 and LDB13 excluding both sides in the bank 1, while the global data bus GDB1 is connected to every other local data buses LDB01 and LDB03 excluding both sides in the bank 0, and to every other local data bus LDB10, LDB12 and LDB14 including both sides. Further, bit line patterns obliquely traversing sense amplifier rows are reverse to each other with respect to the banks 0 and 1

摘要翻译： 全局数据总线GDB0和GDB1与组1中本地数据总线LDB00至LDB04的连接与组0中的数据总线相反。也就是说，全局数据总线GDB0连接到每个其他本地数据总线LDB00，LDB02和LDB04，包括 以及除了存储体1中的两侧以外的其他本地数据总线LDB11，LDB13，而全局数据总线GDB1连接到除了存储体0中的两侧以外的其他本地数据总线LDB01，LDB03， 以及包括两侧的其他本地数据总线LDB10，LDB12和LDB14。 此外，倾斜地遍历读出放大器行的位线模式相对于存储体0和1彼此相反