公开(公告)号：US12229867B2

公开(公告)日：2025-02-18

申请号：US18310015

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Darrel Palke ,  Sherine Abdelhak ,  Jill Boyce ,  Varghese George ,  Scott Janus ,  Adam Lake ,  Zhijun Lei ,  Zhengmin Li ,  Mike MacPherson ,  Carl Marshall ,  Selvakumar Panneer ,  Prasoonkumar Surti ,  Karthik Veeramani ,  Deepak Vembar ,  Vallabhajosyula Srinivasa Somayazulu

IPC: G06T17/20 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/40

Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

公开(公告)号：US20250037359A1

公开(公告)日：2025-01-30

申请号：US18793166

申请日：2024-08-02

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T15/50 ,  G06T1/60 ,  G06T11/20 ,  G06T11/40 ,  G06T15/80

Abstract: Systems, apparatuses and methods may provide for technology that selects an anti-aliasing mode for a vertex of a primitive based on a parameter associated with the vertex and generates a coverage mask based on the selected anti-aliasing mode. Additionally, one or more pixels corresponding to the vertex may be shaded based at least partly on the coverage mask, wherein the selected anti-aliasing mode varies across a plurality of vertices in the primitive.

公开(公告)号：US12198221B2

公开(公告)日：2025-01-14

申请号：US18436494

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F8/41 ,  G06F9/455 ,  G06F9/50 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

公开(公告)号：US20240394956A1

公开(公告)日：2024-11-28

申请号：US18675746

申请日：2024-05-28

Applicant: Intel Corporation

Inventor： Sven Woop ,  Michael J. Doyle ,  Sreenivas Kothandaraman ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Carsten Benthin ,  Prasoonkumar Surti ,  Holger Gruen ,  Stephen Junkins ,  Adam Lake ,  Bret G. Alfieri ,  Gabor Liktor ,  Joshua Barczak ,  Won-Jong Lee

IPC: G06T15/06 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.

公开(公告)号：US20240355032A1

公开(公告)日：2024-10-24

申请号：US18436688

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Atsuo Kuwahara ,  Deepak S. Vembar ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Prasoonkumar Surti ,  Murali Ramadoss

IPC: G06T15/00 ,  G06F9/50 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10

CPC classification number: G06T15/005 ,  G06F9/5027 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T2215/16

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.

公开(公告)号：US12086120B2

公开(公告)日：2024-09-10

申请号：US18066436

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Karol Szerszen ,  Eric Liskay ,  Karthik Vaidyanathan

IPC: G06F16/22 ,  G06N20/00 ,  G06T1/20

CPC classification number: G06F16/2237 ,  G06N20/00 ,  G06T1/20

Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.

公开(公告)号：US12056906B2

公开(公告)日：2024-08-06

申请号：US18466141

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Ben Ashbaugh ,  Prasoonkumar Surti ,  Pradeep Ramani ,  Rama Harihara ,  Jerin C. Justin ,  Jing Huang ,  Xiaoming Cui ,  Timothy B. Costa ,  Ting Gong ,  Elmoustapha Ould-ahmed-vall ,  Kumar Balasubramanian ,  Anil Thomas ,  Oguz H. Elibol ,  Jayaram Bobba ,  Guozhong Zhuang ,  Bhavani Subramanian ,  Gokce Keskin ,  Chandrasekaran Sakthivel ,  Rajesh Poornachandran

IPC: G06F12/02 ,  G06T9/00 ,  G06T15/00

CPC classification number: G06T9/002 ,  G06F12/023 ,  G06T15/005 ,  G06F2212/302 ,  G06F2212/401

Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.

公开(公告)号：US20240257433A1

公开(公告)日：2024-08-01

申请号：US18414841

申请日：2024-01-17

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Karthik Vaidyanathan ,  Saikat Mandal ,  Michael Norris

IPC: G06T15/00 ,  G06F3/06 ,  G06T15/06

CPC classification number: G06T15/005 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06T15/06

Abstract: Apparatus and method for asynchronous ray tracing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes including a root node, a plurality of internal nodes, and a plurality of leaf nodes comprising primitives, wherein each internal node comprises a child node to either the root node or another internal node and each leaf node comprises a child node to an internal node; a first storage bank to be arranged as a first plurality of entries; a second storage bank to be arranged as a second plurality of entries, wherein each entry of the first plurality of entries and the second plurality of entries is to store a ray to be traversed through the BVH; an allocator circuit to distribute an incoming ray to either the first storage bank or the second storage bank based on a relative numbers of rays currently stored in the first and second storage banks; and traversal circuitry to alternate between selecting a next ray from the first storage bank and the second storage bank, the traversal circuitry to traverse the next ray through the BVH by reading a next BVH node from a top of a BVH node stack and determining whether the next ray intersects the next BVH node.

公开(公告)号：US20240256456A1

公开(公告)日：2024-08-01

申请号：US18391346

申请日：2023-12-20

Applicant: Intel Corporation

Inventor： Vikranth Vemulapalli ,  Lakshminarayanan Striramassarma ,  Mike MacPherson ,  Aravindh Anantaraman ,  Ben Ashbaugh ,  Murali Ramadoss ,  William B. Sadler ,  Jonathan Pearce ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter, Jr. ,  Prasoonkumar Surti ,  Nicolas Galoppo von Borries ,  Joydeep Ray ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Altug Koker ,  Sungye Kim ,  Subramaniam Maiyuran ,  Valentin Andrei

IPC: G06F12/0862 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F12/0862 ,  G06T1/20 ,  G06T1/60 ,  G06F2212/602 ,  G06F2212/608

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the Li cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：US11915357B2

公开(公告)日：2024-02-27

申请号：US16820483

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Abhishek Appu ,  Vasanth Ranganathan ,  Joydeep Ray ,  Prasoonkumar Surti

IPC: G06T15/06 ,  G06T15/00

CPC classification number: G06T15/005 ,  G06T15/06

Abstract: Apparatus and method for stack throttling. For example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of ray shaders and generate a plurality of primary rays and a corresponding plurality of ray messages; a first in first out (FIFO) buffer to queue the ray messages generated by the EUs; a cache to store one or more of the plurality of primary rays; a memory-backed stack to store a first subset of the plurality of ray messages in a corresponding plurality of entries; memory-backed stack management circuitry to either store a second subset of the plurality of ray messages to the memory-backed stack, or to temporarily store the one or more the second subset of the plurality of ray messages to a memory subsystem based, at least in part, on a number of entries currently occupied by ray messages in the memory-backed stack; and ray traversal circuitry to read a next ray message from the memory-backed stack, retrieve a next primary ray identified by the ray message from the cache or a memory subsystem, and perform traversal operations on the next primary ray.