公开(公告)号：US20210151449A1

公开(公告)日：2021-05-20

申请号：US17133387

申请日：2020-12-23

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Karthik Balakrishnan ,  Tak Ning ,  Bahman Hekmatshoartabari

IPC: H01L27/11541 ,  H01L29/788 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/28

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

公开(公告)号：US10998444B2

公开(公告)日：2021-05-04

申请号：US16272617

申请日：2019-02-11

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Karthik Balakrishnan ,  Tak Ning ,  Bahman Hekmatshoartabari

IPC: H01L29/78 ,  H01L21/283 ,  H01L29/66 ,  H01L21/02 ,  H01L27/11551 ,  H01L21/8234 ,  H01L27/112

Abstract: A stacked FinFET mask-programmable read only memory (ROM) is provided. The stacked FinFET mask-programmable ROM includes a fin structure extending upward from an insulator layer. In accordance with the present application, the fin structure includes, from bottom to top, a lower programmable semiconductor fin portion having a first threshold voltage, an insulator fin portion, and an upper programmable semiconductor fin portion having a second threshold voltage. A lower gate structure contacts a sidewall of the lower programmable semiconductor fin portion, and an upper gate structure contacts a sidewall of the upper programmable semiconductor fin portion.

公开(公告)号：US10957707B2

公开(公告)日：2021-03-23

申请号：US16391982

申请日：2019-04-23

Applicant: International Business Machines Corporation

Inventor： Jeng-Bang Yau ,  Alexander Reznicek ,  Bahman Hekmatshoartabari ,  Karthik Balakrishnan

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/786 ,  G01T1/02 ,  H01L27/11573

Abstract: The dosimeter has two vertical field effect transistors (VFETs), each VFET with a bottom and top source/drain and channel between them. An implanted charge storage region material lies between and in contact with each of the vertical channels. A trapped charge is within the implanted charge storage region. The amount of the trapped charge is related to an amount of radiation that passes through the implanted charge storage region.

公开(公告)号：US10903210B2

公开(公告)日：2021-01-26

申请号：US14704760

申请日：2015-05-05

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/10 ,  H01L29/167 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/223 ,  H01L21/324 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the IC. Fins on pedestals are defined, e.g., with a hard mask, in a fin layer on a semiconductor wafer and spaces between the pedestals are filled with dielectric material, e.g., shallow trench isolation (STI). Sacrificial sidewalls are formed along the sides of fins and pedestal sub-fins sidewalls are re-exposed. Pedestal sub-fins are doped with a punch-though dopant and punch-though dopant is diffused into the sub-fins and the bottoms of fins. After removing the hard mask and sacrificial sidewalls, metal FET gates are formed on the fins.

公开(公告)号：US10886333B2

公开(公告)日：2021-01-05

申请号：US16290176

申请日：2019-03-01

Applicant: International Business Machines Corporation

Inventor： Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Karthik Balakrishnan

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A method for manufacturing a semiconductor memory device includes forming a plurality of source lines spaced apart from each other on a dielectric layer, forming a plurality of spacers on sides of the plurality of source lines, and forming a plurality of drain lines on the dielectric layer adjacent the plurality of source lines including the plurality of spacers formed thereon. In the method, a metal oxide layer is formed on the plurality of source lines and on the plurality of drain lines, and a plurality of gate lines are formed on the metal oxide layer. The plurality of gate lines are oriented perpendicular to the plurality of drain lines and the plurality of source lines.

公开(公告)号：US10886275B2

公开(公告)日：2021-01-05

申请号：US16266544

申请日：2019-02-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alexander Reznicek ,  Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Clint Oteri

IPC: H01L21/00 ,  H01L27/108 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06

Abstract: A memory device is provided that includes a bilayer nanosheet channel layer including a silicon (Si) layer and a silicon germanium (SiGe) layer; and a common gate structure for biasing each of the silicon layer and the silicon germanium layer of the bilayer nanosheet channel layer to provide one of the silicon layer and the silicon germanium layer is biased in accumulation and one of the first layer and the second layer biased in inversion. The memory devices also includes a floating body region on a front face or rear face of the bilayer nanosheet channel layer.

公开(公告)号：US20200259013A1

公开(公告)日：2020-08-13

申请号：US16272617

申请日：2019-02-11

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Karthik Balakrishnan ,  Tak Ning ,  Bahman Hekmatshoartabari

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/283 ,  H01L21/8234 ,  H01L27/112 ,  H01L27/11551

Abstract: A stacked FinFET mask-programmable read only memory (ROM) is provided. The stacked FinFET mask-programmable ROM includes a fin structure extending upward from an insulator layer. In accordance with the present application, the fin structure includes, from bottom to top, a lower programmable semiconductor fin portion having a first threshold voltage, an insulator fin portion, and an upper programmable semiconductor fin portion having a second threshold voltage. A lower gate structure contacts a sidewall of the lower programmable semiconductor fin portion, and an upper gate structure contacts a sidewall of the upper programmable semiconductor fin portion.

公开(公告)号：US20200212228A1

公开(公告)日：2020-07-02

申请号：US16814196

申请日：2020-03-10

Applicant: International Business Machines Corporation

Inventor： Pouya Hashemi ,  Kangguo Cheng ,  Alexander Reznicek ,  Karthik Balakrishnan

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/10

Abstract: A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.

公开(公告)号：US10671958B2

公开(公告)日：2020-06-02

申请号：US16406157

申请日：2019-05-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Keith A. Jenkins ,  Barry P. Linder

IPC: G06Q10/06 ,  G06K9/00 ,  G06K9/62

Abstract: A computer-implemented method for analyzing customer satisfaction is presented. The computer-implemented method may include capturing visual images related to individuals and order consumables, determining, by a processor, at least one measurable metric to predict variations indicating different satisfaction levels, and dynamically refining parameters if the variations exceed one or more thresholds. The computer-implemented method further includes receiving the captured visual images of the individuals and the order consumables by least one camera in communication with the processor.

公开(公告)号：US10580901B2

公开(公告)日：2020-03-03

申请号：US15255621

申请日：2016-09-02

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L21/336 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

Abstract: A method of forming a semiconductor device and resulting structures having stacked vertical field effect transistors (VFETs) connected in series. A first semiconductor fin and a second semiconductor fin are formed on a doped region of a substrate. A shared gate is formed over a channel region of the first semiconductor fin and a channel region of the second semiconductor fin. A shared epitaxy region is formed on a surface of the first semiconductor fin and a surface of the second semiconductor fin.