公开(公告)号：US20170329003A1

公开(公告)日：2017-11-16

申请号：US15156061

申请日：2016-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Li-Wen Hung ,  Reinaldo Vega

IPC: G01S15/04

CPC classification number: G01S15/04 ,  G01S15/74 ,  H04B11/00

Abstract: A system and method are provided. The system includes a data reader having a processor for performing a signal frequency analysis, an ultrasound transmitter for transmitting ultrasound signals, and an ultrasound receiver for receiving reflected ultrasound signals. The system further includes a movable reflector for receiving the ultrasound signals and reflecting the ultrasounds signals back to the receiver (a) as the reflected ultrasound signals without modulation when the reflector is stationary and (b) as the reflected ultrasound signals with modulation when the reflector is mobile. The system also includes a chip for storing a specification of motion states for the reflector. The processor performs the signal frequency analysis to detect a presence or an absence of modulated frequency components in a received ultrasound signal and outputs a first value or a second value respectively depending upon whether the presence or the absence of the modulated frequency components is detected.

公开(公告)号：US20170317177A1

公开(公告)日：2017-11-02

申请号：US15431807

申请日：2017-02-14

Applicant: International Business Machines Corporation

Inventor： Hari V. Mallela ,  Robert R. Robison ,  Reinaldo Vega ,  Rajasekhar Venigalla

IPC: H01L29/417 ,  H01L29/78 ,  H01L23/485

CPC classification number: H01L29/41741 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78687 ,  H01L29/78696

Abstract: Semiconductor devices having vertical FET (field effect transistor) devices with metallic source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a semiconductor device includes a first source/drain region formed on a semiconductor substrate, a vertical semiconductor fin formed on the first source/drain region, a second source/drain region formed on an upper surface of the vertical semiconductor fin, a gate structure formed on a sidewall surface of the vertical semiconductor fin, and an insulating material that encapsulates the vertical semiconductor fin and the gate structure. The first source/drain region comprises a metallic layer and at least a first epitaxial semiconductor layer. For example, the metallic layer of the first source/drain region comprises a metal-semiconductor alloy such as silicide.

公开(公告)号：US20150325483A1

公开(公告)日：2015-11-12

申请号：US14270791

申请日：2014-05-06

Applicant: International Business Machines Corporation

Inventor： Cung Tran ,  Emre Alptekin ,  Viraj Sardesai ,  Reinaldo Vega

IPC: H01L21/8234 ,  H01L21/32 ,  H01L29/49 ,  H01L21/285 ,  H01L21/3105 ,  H01L49/02 ,  H01L23/525 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/31055 ,  H01L21/32 ,  H01L21/76897 ,  H01L21/823443 ,  H01L23/5228 ,  H01L23/5256 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of present invention provide a method of forming metal resistor. The method includes forming a first and a second structure on top of a semiconductor substrate in a replacement-metal-gate process to have, respectively, a sacrificial gate and spacers adjacent to sidewalls of the sacrificial gate; covering the second structure with an etch-stop mask; replacing the sacrificial gate of the first structure with a replacement metal gate; removing the etch-stop mask to expose the sacrificial gate of the second structure; forming a silicide in the second structure as a metal resistor; and forming contacts to the silicide. In one embodiment, forming the silicide includes siliciding a top portion of the sacrificial gate of the second structure to form the metal resistor. In another embodiment, forming the silicide includes removing the sacrificial gate of the second structure to expose and silicide a channel region underneath thereof.

Abstract translation: 本发明的实施例提供一种形成金属电阻器的方法。 该方法包括在替代金属栅极工艺中在半导体衬底的顶部上形成第一和第二结构，以分别具有与牺牲栅极的侧壁相邻的牺牲栅极和间隔物; 用蚀刻停止掩模覆盖第二结构; 用替换金属浇口代替第一结构的牺牲栅极; 去除蚀刻停止掩模以暴露第二结构的牺牲栅极; 在第二结构中形成作为金属电阻器的硅化物; 并形成与硅化物的接触。 在一个实施例中，形成硅化物包括硅化第二结构的牺牲栅极的顶部以形成金属电阻器。 在另一个实施例中，形成硅化物包括去除第二结构的牺牲栅极以暴露其下方的沟道区域并硅化。

公开(公告)号：US20250125250A1

公开(公告)日：2025-04-17

申请号：US18485346

申请日：2023-10-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Reinaldo Vega ,  Lawrence A. Clevenger ,  Ruilong Xie ,  Brent A. Anderson

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a plurality of lower metal lines in a first metal level; a transition via directly on top of the plurality of lower metal lines; and an upper metal line directly on top of the transition via and the upper metal line being in a second metal level and orthogonal to the plurality of lower metal lines, where at least a first lower metal line of the plurality of lower metal lines has a recessed region and a rest region, the recessed region is directly underneath the transition via and filled with a dielectric material; and isolates the rest region of the first lower metal line from the transition via. A method of manufacturing the same is also provided.

公开(公告)号：US20250056839A1

公开(公告)日：2025-02-13

申请号：US18231884

申请日：2023-08-09

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  Julien Frougier ,  Ruilong Xie ,  Jingyun Zhang

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/775

Abstract: A semiconductor structure is provided that includes a tunable and shared non-conductive layer as part of a gate stack of at least a pair of nanosheet GAA transistors with a shared metal gate electrode. The semiconductor structure has a tunable non-conductive material/gate dielectric area ratio where the non-conductive material is not constrained to a periphery of the nanosheet stack cross section.

公开(公告)号：US20250054863A1

公开(公告)日：2025-02-13

申请号：US18448933

申请日：2023-08-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Takashi Ando ,  David Wolpert

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device architecture includes a substrate and a device region including active components carried by the substrate. A plurality of tracks are on the substrate including conductive lines connecting power and signals to the active components in the device region. A first track includes a plurality of segments of a conductive line. A first segment in the first track delivers power to the device region. A second segment in the first track delivers a signal to the device region. The first segment and the second segment are arranged in the same first track.

公开(公告)号：US12207573B2

公开(公告)日：2025-01-21

申请号：US17475970

申请日：2021-09-15

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Kevin W. Brew ,  Takashi Ando ,  Reinaldo Vega

IPC: H10N70/00 ,  H10B63/10 ,  H10N70/20

Abstract: A memory, system, and method to improve integration density while maintaining thermal efficiency through a phase change memory cell with a superlattice based thermal barrier. The phase change memory may include a bottom electrode. The phase change memory may also include an active phase change material. The phase change memory may also include a superlattice thermal barrier proximately connected to the active phase change material. The phase change memory may also include a top electrode proximately connected to the superlattice thermal barrier. The system may include the phase change memory cell. The method for forming a phase change memory may include depositing an active phase change material on a bottom electrode. The method may also include depositing a superlattice thermal barrier proximately connected to the active phase change material. The method may also include depositing a top electrode proximately connected to the superlattice thermal barrier.

公开(公告)号：US20240421087A1

公开(公告)日：2024-12-19

申请号：US18334606

申请日：2023-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Ruilong Xie ,  Albert M. Chu ,  Nicholas Anthony Lanzillo ,  Brent A. Anderson ,  Reinaldo Vega

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

Abstract: According to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. The second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. A first backside signal line and a second backside signal line are located at a cell boundary of the first nanodevice. A first gap exists between the first backside signal line and the second backside signal line.

公开(公告)号：US20240421078A1

公开(公告)日：2024-12-19

申请号：US18333863

申请日：2023-06-13

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Ruilong Xie ,  Lawrence A. Clevenger ,  Reinaldo Vega

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor structure includes a plurality of vertical transport field effect transistors, and an interconnect structure connected to one of respective source/drain regions of at least two vertical transport field effect transistors of the plurality of vertical transport field effect transistors and respective gate regions of the at least two vertical transport field effect transistors. The interconnect structure comprises a damascene portion, and a subtractive portion disposed on the damascene portion.

公开(公告)号：US20240421038A1

公开(公告)日：2024-12-19

申请号：US18337318

申请日：2023-06-19

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Brent A. Anderson ,  Ruilong Xie ,  Albert M. Chu ,  Lawrence A. Clevenger ,  Reinaldo Vega

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor structure includes a stacked device structure containing a first device and a second device over the first device in a stacked configuration. The semiconductor structure further includes a first backside contact connected to the first device and a first backside power line. The semiconductor structure further includes a second backside contact connected to the second device and a second backside power line.