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公开(公告)号：US20090182984A1
公开(公告)日：2009-07-16
申请号：US11972714
申请日：2008-01-11
IPC分类号： G06F9/30
CPC分类号： G06F9/30054 , G06F9/30167 , G06F9/324 , G06F9/342 , G06F9/355
摘要： A method, system and program product for an execute relative instruction, which when executed fetches and executes a target instruction at a relative address and then returns processing to the next instruction following the execute relative instruction. The relative address is formed by adding the value of the program counter to a sign extended immediate field. The fetched target instruction is optionally modified before execution by OR'ing bits into predetermined bits of the target instruction.
摘要翻译： 一种用于执行相关指令的方法，系统和程序产品，其在执行时在相对地址处获取并执行目标指令，然后在执行相关指令之后向下一个指令返回处理。 通过将程序计数器的值添加到符号扩展的立即数字段来形成相对地址。 所获取的目标指令在执行之前可选地被修改以将位对准目标指令的预定位。
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102.发明申请公开(公告)号：US20090182981A1
公开(公告)日：2009-07-16
申请号：US11972679
申请日：2008-01-11
IPC分类号： G06F9/315
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/30189 , G06F9/342
摘要： A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.
摘要翻译： 旋转，然后操作具有T位的指令被执行，其中第一寄存器中的第一操作数旋转一个量，并且对旋转的第一操作数的选定部分执行布尔运算，并且在第二寄存器中执行第二操作数 。 如果T位为“0”，则将布尔运算结果的选定部分插入到第二寄存器的第二个操作数的相应位中。 如果T位为“1”，除了插入的位之外，所转动的第一个操作数的选定部分以外的其他位被保存在第二个寄存器中。
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公开(公告)号：US20090182972A1
公开(公告)日：2009-07-16
申请号：US11972697
申请日：2008-01-11
申请人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/1027
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.
摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的索引部分用于引用转换表中的条目。 如果启用了转换表条目中包含的格式控制字段，则表项包含大小至少为1M字节的大块数据的帧地址。 然后将帧地址与虚拟地址的偏移部分组合以形成主存储器或存储器中的小4K字节数据块的转换地址。
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公开(公告)号：US20090182971A1
公开(公告)日：2009-07-16
申请号：US11972688
申请日：2008-01-11
申请人： DAN F. GREINER , Charles W. Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： DAN F. GREINER , Charles W. Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/30047 , G06F12/0215 , G06F12/1009 , G06F12/1036 , G06F12/145 , G06F2212/1052 , G06F2212/654 , G06F2212/656 , G06F2212/68
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field.
摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，首先获得要被翻译的虚拟地址，并且获得翻译表层级的翻译表的初始起始地址。 基于获得的初始来源，获得段表条目。 段表项被配置为包含格式控制和访问有效性字段。 如果启用格式控制和访问有效性字段，则段表条目还包含访问控制字段，提取保护字段和段帧绝对地址。 仅当访问控制字段与程序状态字或正在执行的程序指令的操作数提供的程序访问键匹配时，才允许存储操作。 如果与虚拟地址相关联的程序访问密钥等于段访问控制字段，则允许获取操作。
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公开(公告)号：US20090182942A1
公开(公告)日：2009-07-16
申请号：US11972675
申请日：2008-01-11
申请人： Dan F. Greiner , Timothy J. Slegel
发明人： Dan F. Greiner , Timothy J. Slegel
IPC分类号： G06F12/08
CPC分类号： G06F9/30145 , G06F9/30047 , G06F9/30058 , G06F9/30167 , G06F9/322
摘要： A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.
摘要翻译： 一种用于指定目标缓存高速缓存级别和感兴趣的目标高速缓存属性的用于获得一个或多个目标高速缓存的高速缓存属性的计算机体系结构的设施和缓存机器指令。 所请求的高速缓存属性被保存在一个寄存器中。
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106.发明申请Register Indirect Access of Program Floating Point Registers by Millicode 失效通过Millicode寄存器间接访问程序浮点寄存器公开(公告)号：US20080126759A1
公开(公告)日：2008-05-29
申请号：US11531301
申请日：2006-09-13
IPC分类号： G06F9/302
CPC分类号： G06F9/3017 , G06F9/35
摘要： Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.
摘要翻译： 当在硬件中实现其功能不具有成本效益时，复杂的浮点指令在毫秒控制下执行。 使用millicode例程执行复杂指令的一个缺点是确定和访问指令操作数对于millicode性能来说是昂贵的。 要确定源和目标位置是什么，解释说明文本。 此外，必须修改millicode指令流以访问操作数数据，并将结果写入由复杂浮点指令指定的程序寄存器。 本发明通过向编程浮点寄存器提供寄存器间接访问的毫代码来克服这些缺点。
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公开(公告)号：US07082550B2
公开(公告)日：2006-07-25
申请号：US10435914
申请日：2003-05-12
IPC分类号： G06F11/16
CPC分类号： G06F11/1695 , G06F11/1641
摘要： A processor responsive to a clock cycle includes a base-unit, a mirror-unit that is a duplicate instance of the base-unit, a non-duplicate-unit in signal communication with the base and mirror units, a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle, and a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clock cycle. The non-duplicate-unit includes a comparator for comparing the output signals of the base and mirror units.
摘要翻译： 响应于时钟周期的处理器包括基本单元，作为基本单元的重复实例的镜像单元，与基础单元和镜像单元进行信号通信的非重复单元，第一分段寄存器，其布置在 用于将输入信号延迟至少一个时钟周期的反射镜单元的输入，以及设置在镜单元的输出处的第二分段寄存器，用于将其输出信号延迟至少一个时钟周期。 非重复单元包括用于比较基座和反射镜单元的输出信号的比较器。
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108.发明授权公开(公告)号：US07082517B2
公开(公告)日：2006-07-25
申请号：US10435806
申请日：2003-05-12
CPC分类号： G06F9/3017 , G06F9/3836 , G06F9/3885
摘要： In a computer system for use as a symetrical multiprocessor, a superscalar microprocessor apparatus allows dispatching and executing multi-cycle and complex instructions Some control signals are generated in the dispatch unit and dispatched with the instruction to the Fixed Point Unit (FXU). Multiple execution pipes correspond to the instruction dispatch ports and the execution unit is a Fixed Point Unit (FXU) which contains three execution dataflow pipes (X, Y and Z) and one control pipe (R). The FXU logic then execute these instructions on the available FXU pipes. This results in optimum performance with little or no other complications. The presented technique places the flexibility of how these instructions will be executed in the FXU, where the actual execution takes place, instead of in the instruction decode or dispatch units or cracking by the compiler.
摘要翻译： 在用作对称多处理器的计算机系统中，超标量微处理器装置允许调度和执行多周期和复杂指令。在调度单元中生成一些控制信号，并且通过指令发送到定点单元（FXU）。 多个执行管道对应于指令调度端口，执行单元是包含三个执行数据流管道（X，Y和Z）和一个控制管道（R）的定点单元（FXU）。 然后，FXU逻辑在可用的FXU管道上执行这些说明。 这导致最佳性能，很少或没有其他并发症。 所提出的技术使得如何在实际执行的FXU中执行这些指令的灵活性，而不是在指令解码或调度单元中或由编译器破解。
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公开(公告)号：US06996698B2
公开(公告)日：2006-02-07
申请号：US10435961
申请日：2003-05-12
IPC分类号： G06F12/00
CPC分类号： G06F12/1475 , G06F12/1036
摘要： Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that fetching of storage keys is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of addresses, which indicates whether the fetching can continue. If fetching can continue, the restriction is ignored.
摘要翻译： 在某些情况下，计算环境的处理限制被过滤和阻止，使处理继续，尽管有限制。 一个限制包括响应于缓冲区未命中而禁止取出存储密钥的指示。 当计算环境的处理单元满足该限制时，它执行地址的比较，其指示获取是否可以继续。 如果提取可以继续，限制将被忽略。
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公开(公告)号：US5282210A
公开(公告)日：1994-01-25
申请号：US891521
申请日：1992-06-01
CPC分类号： H04J3/047
摘要： A time-division multiplex system is disclosed where the data from two sources is coupled over a multiplexer controller by a generator comprising an XOR gate and a pair of latches where the output of both latches are coupled to the XOR gate and an inverter at the input of each latch. One of the latches is gated by a master clock signal and the other latch is gated by a clocked signal skewed approximately one-half clock cycle.
摘要翻译： 公开了一种时分多路复用系统，其中来自两个源的数据通过多路复用器控制器由包括XOR门和一对锁存器的发生器耦合，其中两个锁存器的输出耦合到XOR门和在输入端的反相器 的每个闩锁。 一个锁存器由主时钟信号门控，另一个锁存器由大约半个时钟周期的时钟信号门控。
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