公开(公告)号：US20240089147A1

公开(公告)日：2024-03-14

申请号：US18513565

申请日：2023-11-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Richard Graham ,  Lion Levi ,  Gil Bloch ,  Daniel Marcovitch ,  Noam Bloch ,  Yong Qin ,  Yaniv Blumenfeld ,  Eitan Zahavi

IPC: H04L12/40 ,  G06F12/02 ,  H04B7/0456 ,  H04L12/44 ,  H04W24/10 ,  H04W88/06

CPC classification number: H04L12/40182 ,  G06F12/0246 ,  H04B7/0456 ,  H04L12/44 ,  H04W24/10 ,  H04W88/06

Abstract: A method includes providing a plurality of processes interconnected by a network, each of the plurality of processes being configured to hold a block of data destined for others of the plurality of processes. A set of data for all-to-all data exchange is received from one or more of the processes. The set of data is configured as a plurality of blocks of data in a matrix as matrix data, the matrix being distributed among the plurality of processes. The matrix data is transposed by changing the position of selected blocks of data of the plurality of blocks of data relative to the other blocks of data of the plurality of the blocks of data, without changing the structure of each of the blocks of data. The transposed matrix data is over the network and is then received, repacked, and conveyed to destination processes.

公开(公告)号：US11909855B2

公开(公告)日：2024-02-20

申请号：US18075460

申请日：2022-12-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Miriam Menes ,  Noam Bloch ,  Adi Menachem ,  Idan Burstein ,  Ariel Shahar ,  Maxim Fudim

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32

CPC classification number: H04L9/0625 ,  H04L9/0861 ,  H04L9/3247

Abstract: In one embodiment, data communication apparatus includes packet processing circuitry to receive data from a memory responsively to a data transfer request, and cryptographically process the received data in units of data blocks using a block cipher so as to add corresponding cryptographically processed data blocks to a sequence of data packets, the sequence including respective ones of the cryptographically processed data blocks having block boundaries that are not aligned with payload boundaries of respective one of the packets, such that respective ones of the cryptographically processed data blocks are divided into two respective segments, which are contained in successive respective ones of the packets in the sequence, and a network interface which includes one or more ports for connection to a packet data network and is configured to send the sequence of data packets to a remote device over the packet data network via the one or more ports.

公开(公告)号：US11848837B2

公开(公告)日：2023-12-19

申请号：US17504517

申请日：2021-10-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Aviad Levy ,  Lion Levi ,  Noam Bloch ,  Ortal Bashan

IPC: H04L43/06 ,  H04L43/04 ,  H04L67/025

CPC classification number: H04L43/06 ,  H04L43/04 ,  H04L67/025

Abstract: A network device includes processing circuitry and one or more ports. The one or more ports are configured to connect to a communication network. The processing circuitry is configured to receive a packet originating from a network node running an application program, the packet includes application-level metadata relating to the application program, to generate telemetry data based at least on the application-level metadata, and to transmit the telemetry data via one of the ports, over the communication network.

公开(公告)号：US11683266B2

公开(公告)日：2023-06-20

申请号：US17963216

申请日：2022-10-11

Applicant: Mellanox Technologies, Ltd.

Inventor： Boris Pismenny ,  Miriam Menes ,  Idan Burstein ,  Liran Liss ,  Noam Bloch ,  Ariel Shahar

IPC: H04L45/00 ,  H04L45/42 ,  G06F11/10 ,  H04L69/163 ,  H04L69/22

CPC classification number: H04L45/566 ,  G06F11/1004 ,  H04L45/38 ,  H04L45/42 ,  H04L69/163 ,  H04L69/22

Abstract: A system includes a host processor, which has a host memory and is coupled to store data in a non-volatile memory in accordance with a storage protocol. A network interface controller (NIC) receives data packets conveyed over a packet communication network from peer computers containing, in payloads of the data packets, data records that encode data in accordance with the storage protocol for storage in the non-volatile memory. The NIC processes the data records in the data packets that are received in order in each flow from a peer computer and extracts and writes the data to the host memory, and when a data packet arrives out of order, writes the data packet to the host memory without extracting the data and processes the data packets in the flow so as to recover context information for use in processing the data records in subsequent data packets in the flow.

公开(公告)号：US20230141761A1

公开(公告)日：2023-05-11

申请号：US18090538

申请日：2022-12-29

Applicant: Mellanox Technologies, Ltd.

Inventor： Or Gerlitz ,  Noam Bloch ,  Gal Yefet

IPC: H04L67/104 ,  H04L43/062 ,  H04L43/0894 ,  H04L67/00 ,  H04L67/01

CPC classification number: H04L67/1044 ,  H04L43/062 ,  H04L43/0894 ,  H04L67/01 ,  H04L67/34

Abstract: A network device includes a network interface, a host interface, and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host comprising a host processor running a client process. The processing circuitry is configured to receive packets belonging to a message having a message length, the message originating from a peer process, to identify, in at least some of the received packets, application-level information specifying the message length, to determine, based on the identified message length, that the packets of the message already received comprise only a portion of the message, and in response to determining that the client process benefits from receiving less than the entire message, to initiate reporting the packets of the message already received to the client process.

公开(公告)号：US20210344600A1

公开(公告)日：2021-11-04

申请号：US16865567

申请日：2020-05-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Avi Urman ,  Lior Narkis ,  Noam Bloch ,  Eyal Srebro ,  Shay Aisman

IPC: H04L12/801 ,  H04L12/835 ,  H04L12/823

Abstract: A network adapter includes a host interface, a network interface, a memory and packet processing circuitry. The memory holds a shared buffer and multiple queues allocated to the multiple host processors. The packet processing circuitry is configured to receive from the network interface data packets destined to the host processors, to store payloads of at least some of the data packets in the shared buffer, to distribute headers of at least some of the data packets to the queues, to serve the data packets to the host processors by applying scheduling among the queues, to detect congestion in the data packets destined to a given host processor among the host processors, and, in response to the detected congestion, to mitigate the congestion in the data packets destined to the given host processor, while retaining uninterrupted processing of the data packets destined to the other host processors.

公开(公告)号：US11088966B2

公开(公告)日：2021-08-10

申请号：US16672682

申请日：2019-11-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Adi Menachem ,  Alex Shpiner ,  Noam Bloch ,  Eitan Zahavi ,  Idan Burstein ,  Dror Bohrer ,  Roee Moyal

IPC: H04L1/00 ,  H04L12/931 ,  H04L12/861 ,  H04L12/851 ,  H04L12/935

Abstract: A network adapter includes a host interface and circuitry. The host interface is configured to connect locally between the network adapter and a host via a bus. The circuitry is configured to receive from one or more source nodes, over a communication network to which the network adapter is coupled, multiple packets destined to the host, and temporarily store the received packets in a queue of the network adapter, to send the stored packets from the queue to the host over the bus, to monitor a performance attribute of the bus, and in response to detecting, based at least on the monitored performance attribute, an imminent overfilling state of the queue, send a congestion notification to at least one of the source nodes from which the received packets originated.

公开(公告)号：US11055222B2

公开(公告)日：2021-07-06

申请号：US16565510

申请日：2019-09-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Ilan Pardo ,  Noam Bloch

IPC: G06F12/08 ,  G06F12/0831 ,  G06F13/16 ,  G06F13/28 ,  G06F3/06 ,  G06F16/907 ,  G06F9/46

Abstract: Computing apparatus includes a central processing unit (CPU), including at least one core and a cache in physical proximity to the at least one core, with a system memory and a bus connecting the CPU to the memory. A peripheral device is connected to the bus and is configured to write data items via the bus to a buffer in the system memory and to write respective completion reports to the system memory upon writing the data items to the buffer. The peripheral device is configured to detect that the CPU has read a first completion report from the system memory and then read context metadata associated with the first completion report from a given address in the system memory, and is further configured, upon writing a second completion report subsequent to the first completion report and associated with the same context metadata, to stash the second completion report and the context metadata from the given address to the cache.

公开(公告)号：US20210073130A1

公开(公告)日：2021-03-11

申请号：US16565510

申请日：2019-09-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Ilan Pardo ,  Noam Bloch

IPC: G06F12/0831 ,  G06F13/16 ,  G06F13/28 ,  G06F3/06 ,  G06F9/46 ,  G06F16/907

Abstract: Computing apparatus includes a central processing unit (CPU), including at least one core and a cache in physical proximity to the at least one core, with a system memory and a bus connecting the CPU to the memory. A peripheral device is connected to the bus and is configured to write data items via the bus to a buffer in the system memory and to write respective completion reports to the system memory upon writing the data items to the buffer. The peripheral device is configured to detect that the CPU has read a first completion report from the system memory and then read context metadata associated with the first completion report from a given address in the system memory, and is further configured, upon writing a second completion report subsequent to the first completion report and associated with the same context metadata, to stash the second completion report and the context metadata from the given address to the cache.

公开(公告)号：US10887252B2

公开(公告)日：2021-01-05

申请号：US16181376

申请日：2018-11-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dror Bohrer ,  Noam Bloch ,  Peter Paneah ,  Richard Graham

IPC: G06F15/167 ,  H04L12/879 ,  H04L12/883 ,  H04L12/931 ,  H04L12/861 ,  H04L12/935

Abstract: A network interface device is connected to a host computer by having a memory controller, and a scatter-gather offload engine linked to the memory controller. The network interface device prepares a descriptor including a plurality of specified memory locations in the host computer, incorporates the descriptor in exactly one upload packet, transmits the upload packet to the scatter-gather offload engine via the uplink, invokes the scatter-gather offload engine to perform memory access operations cooperatively with the memory controller at the specified memory locations of the descriptor, and accepts results of the memory access operations.