公开(公告)号：US20250138751A1

公开(公告)日：2025-05-01

申请号：US18939279

申请日：2024-11-06

Applicant: Micron Technology, Inc.

Inventor： Deping He

IPC: G06F3/06

Abstract: Methods, systems, and devices for commands to support adaptive memory systems are described. A memory system may be configured to receive a command to perform an operation on an address of a memory system, the command including an indication of a count of program/erase cycles associated with the address; determine whether the count of program/erase cycles associated with the address satisfies a threshold; adjust a trim parameter for operating the memory system based at least in part on determining that the indication of the count of program/erase cycles satisfies the threshold; and perform the operation associated with the command using the adjusted trim parameter.

公开(公告)号：US12210448B2

公开(公告)日：2025-01-28

申请号：US18037631

申请日：2022-09-01

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu ,  Deping He ,  Kulachet Tanpairoj ,  Hong Lu ,  Chun Sum Yeung

IPC: G06F12/02

Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

公开(公告)号：US12159059B2

公开(公告)日：2024-12-03

申请号：US17818922

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Deping He

IPC: G06F3/06

Abstract: Methods, systems, and devices for commands to support adaptive memory systems are described. A memory system may be configured to receive a command to perform an operation on an address of a memory system, the command including an indication of a count of program/erase cycles associated with the address; determine whether the count of program/erase cycles associated with the address satisfies a threshold; adjust a trim parameter for operating the memory system based at least in part on determining that the indication of the count of program/erase cycles satisfies the threshold; and perform the operation associated with the command using the adjusted trim parameter.

公开(公告)号：US20240345750A1

公开(公告)日：2024-10-17

申请号：US18638471

申请日：2024-04-17

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/3234 ,  G06F1/3296

CPC classification number: G06F3/0634 ,  G06F1/3275 ,  G06F1/3296 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: Methods, systems, and devices for host recovery for a stuck condition of a memory system are described. The host system may transmit a first command for the memory system to transition from a first power mode to a second power mode (e.g., low-power mode). In some cases, the host system may transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system may activate a timer associated with a time-out condition for exiting the second power mode and may determine that a duration indicated by the timer expires. In some examples, the host system may transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

公开(公告)号：US20240329721A1

公开(公告)日：2024-10-03

申请号：US18597462

申请日：2024-03-06

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Jonathan S. Parry

IPC: G06F1/3234 ,  G06F1/3287

CPC classification number: G06F1/3275 ,  G06F1/3287

Abstract: Methods, systems, and devices for shallow hibernate power state are described. A memory system may include a memory array and a controller. The memory system may transition from a first power state having a first current to a second power state having a second current less than the first current, where the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components of the memory array. The memory system may initiate a timer after transitioning from the first power state to the second power state. The memory system may determine the timer satisfies a threshold and transition from the second power state to a third power state having a third current less than the second current based on the timer satisfying the threshold.

公开(公告)号：US20240320153A1

公开(公告)日：2024-09-26

申请号：US18616993

申请日：2024-03-26

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F12/0811 ,  G06F11/10 ,  G06F11/30 ,  G06F12/0882 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F11/1068 ,  G06F11/3037 ,  G06F12/0882 ,  G06F12/0891

Abstract: Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.

公开(公告)号：US20240273023A1

公开(公告)日：2024-08-15

申请号：US18630779

申请日：2024-04-09

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Deping He ,  Min Rui Ma

IPC: G06F12/0804 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G06F12/0804 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G06F2212/1032 ,  G11C16/0483

Abstract: Methods, systems, and devices for techniques for enhanced system performance after retention loss are described. A memory system may program a page of memory cells in response to receiving a power down notification. As part of the programming, the memory system may record an indication of a voltage threshold of the page and power down for a duration of time, during which the memory system may experience retention loss. Upon powering on, the memory device may compare the voltage threshold of the page to the indication stored prior to powering down and determine a voltage offset for one or more blocks of the memory system. In some cases, the memory system may use the voltage offset to determine a starting bin, and may initiate a bin scan to determine a final bin for the one or more blocks.

公开(公告)号：US11983112B2

公开(公告)日：2024-05-14

申请号：US17646253

申请日：2021-12-28

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Deping He ,  Min Rui Ma

IPC: G06F12/00 ,  G06F12/0804 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04

CPC classification number: G06F12/0804 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G06F2212/1032 ,  G11C16/0483

Abstract: Methods, systems, and devices for techniques for enhanced system performance after retention loss are described. A memory system may program a page of memory cells in response to receiving a power down notification. As part of the programming, the memory system may record an indication of a voltage threshold of the page and power down for a duration of time, during which the memory system may experience retention loss. Upon powering on, the memory device may compare the voltage threshold of the page to the indication stored prior to powering down and determine a voltage offset for one or more blocks of the memory system. In some cases, the memory system may use the voltage offset to determine a starting bin, and may initiate a bin scan to determine a final bin for the one or more blocks.

公开(公告)号：US11934692B2

公开(公告)日：2024-03-19

申请号：US17645265

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Deping He

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for write booster buffer and hibernate are described. The memory system may initiate a first operation to enter a first power mode having a lower power consumption than a second power mode. In some cases, the memory system may determine whether a quantity of data stored in a buffer of single-level cells associated with write booster information satisfies a threshold based on initiating the first operation. The memory system may determine whether to perform a second operation to transfer the quantity of data stored in the buffer of single-level cells to a portion of memory comprising multiple level cells based on determining whether the quantity of data satisfies the threshold. The memory system may enter the first power mode based on determining to perform the second operation to transfer the quantity of data from the buffer to the portion of memory.

公开(公告)号：US11899963B2

公开(公告)日：2024-02-13

申请号：US17654552

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Caixia Yang ,  Deping He

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0676 ,  G06F3/0679

Abstract: Methods, systems, and devices for suspension during a multi-plane write procedure are described. A memory system may perform a multi-plane write procedure by writing to a set of planes in parallel. Upon detecting a defective plane in the set of planes, the memory system may suspend writing to the defective plane until writing to the other planes in the set of planes is finished. The memory system may then resume writing to the defective plane.