公开(公告)号：US08790977B2

公开(公告)日：2014-07-29

申请号：US14080417

申请日：2013-11-14

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract translation: 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

公开(公告)号：US08609488B2

公开(公告)日：2013-12-17

申请号：US13869112

申请日：2013-04-24

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

公开(公告)号：US20250142840A1

公开(公告)日：2025-05-01

申请号：US19002398

申请日：2024-12-26

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B63/00 ,  G11C5/12 ,  G11C11/16 ,  G11C11/22 ,  G11C11/401 ,  G11C13/00 ,  H10D30/01 ,  H10D30/63 ,  H10D30/67 ,  H10D84/01 ,  H10D84/03 ,  H10D86/40 ,  H10D86/60 ,  H10N70/00 ,  H10N70/20

Abstract: Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material, and the channel material includes a second, different material.

公开(公告)号：US12283636B2

公开(公告)日：2025-04-22

申请号：US18669237

申请日：2024-05-20

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu

IPC: H01L29/786 ,  H01L29/66

Abstract: A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.

公开(公告)号：US12266660B2

公开(公告)日：2025-04-01

申请号：US18400082

申请日：2023-12-29

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B99/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/788

Abstract: Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.

公开(公告)号：US12219758B2

公开(公告)日：2025-02-04

申请号：US18428325

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Yunfei Gao ,  Sanh D. Tang ,  Deepak Chandra Pandey

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240407154A1

公开(公告)日：2024-12-05

申请号：US18677457

申请日：2024-05-29

Applicant: Micron Technology, Inc.

Inventor： Albert Daen Liao ,  Ting Zhao ,  Cheng Li ,  Ruijing Ge ,  Matthew Jacob Jerry ,  David A. Daycock ,  Kolya Yastrebenetsky ,  Kamal M. Karda

IPC: H10B12/00

Abstract: A variety of applications can include an apparatus having a memory device including digit lines isolated from each other by filling an area directly under the digit line with a dielectric material. The dielectric material can be any insulating material such as oxides or nitrides. The provision of the area directly under each digit line can be accomplished without etching out an entire layer of epitaxially grown regions for the memory cells vertically stacked in a three-dimensional array. In a three-dimensional DRAM, metal plates for capacitors can be isolated in a manner similar to the isolation of digit lines. Such processing can be scalable, which may allow for a three-dimensional DRAM to have hundreds memory cell tiers.

公开(公告)号：US20240389329A1

公开(公告)日：2024-11-21

申请号：US18666358

申请日：2024-05-16

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Kamal M. Karda

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory device, which includes a first memory cell string, a second memory cell string adjacent the first memory cell string, and a control gate. The first memory string includes a first channel structure, a first charge storage structure, and a first dielectric structure between the first channel structure and the first charge storage structure. The second memory cell string includes a second channel structure, a second charge storage structure, and a second dielectric structure between the second channel structure and the second charge storage structure. The control gate is separated from the first charge storage structure by a third dielectric structure and separated from the second channel structure by a fourth dielectric structure. The control gate and the first charge storage structure are between the first channel structure and the second channel structure.

公开(公告)号：US20240373619A1

公开(公告)日：2024-11-07

申请号：US18662659

申请日：2024-05-13

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Srinivas Pulugurtha ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B12/00 ,  G11C11/402

Abstract: Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.

公开(公告)号：US20240313125A1

公开(公告)日：2024-09-19

申请号：US18669237

申请日：2024-05-20

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/66666 ,  H01L29/6675 ,  H01L29/7869

Abstract: A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.