公开(公告)号：US20230362096A1

公开(公告)日：2023-11-09

申请号：US18106953

申请日：2023-02-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Roee Moyal

IPC: H04L47/22 ,  H04L47/263

CPC classification number: H04L47/225 ,  H04L47/263

Abstract: A system includes a device coupled to a processing device. The processing device is to receive a request to execute a plurality of workloads, the request comprising a rate to execute each workload of the plurality of workloads and a parameter value indicating an execution offset. The processing device is further to determine a sequence for executing the plurality of workloads based on receiving the rate and the parameter value, where the sequence is to execute each workload at the respective rate and each workload of the plurality of workloads is executed at a different time based on the parameter value. The processing device is to execute the plurality of workloads in accordance with the sequence upon determining the sequence to execute the plurality of workloads.

公开(公告)号：US20230251899A1

公开(公告)日：2023-08-10

申请号：US17667600

申请日：2022-02-09

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Daniel Marcovitch ,  Natan Manevich ,  Wojciech Wasko ,  Igor Voks

IPC: G06F9/48

CPC classification number: G06F9/4887

Abstract: In one embodiment, a system includes a peripheral device including a hardware clock, and processing circuitry to read a given work request entry stored with a plurality of work request entries in at least one work queue in a memory, the given work request entry including timing data and an operator, the timing data being indicative of a time at which a work request should be executed, retrieve a clock value from the hardware clock, and execute the work request with a workload while execution of the work request is timed responsively to the timing data and the operator and the retrieved clock value.

公开(公告)号：US20230229188A1

公开(公告)日：2023-07-20

申请号：US17578115

申请日：2022-01-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Bar Shapira ,  Ariel Almog ,  Dotan David Levi ,  Natan Manevich ,  Thomas Kernen

IPC: G06F1/10 ,  G06F13/40

CPC classification number: G06F1/10 ,  G06F13/4022 ,  G06F2213/3808

Abstract: A system is disclosed that includes two or more network elements, each comprising a Precision Time Protocol (PTP) Hardware Clock (PHC) that is adjustable based, at least in part, on physical layer frequency information.

公开(公告)号：US11606427B2

公开(公告)日：2023-03-14

申请号：US17120313

申请日：2020-12-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Avraham Ganor ,  Arnon Sattinger ,  Natan Manevich ,  Reuven Kogan ,  Artiom Tsur ,  Ariel Almog ,  Bar Shapira

IPC: H04L67/1095 ,  G06F1/12 ,  G06F1/14

Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.

公开(公告)号：US11500808B1

公开(公告)日：2022-11-15

申请号：US17384834

申请日：2021-07-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avraham Ganor ,  Peter Paneah ,  Dotan David Levi

IPC: G06F13/42 ,  G06F13/40 ,  G06F11/14 ,  G06F1/3234 ,  G06F9/448

Abstract: A peripheral device includes a bus interface and circuitry. The bus interface is configured to connect to a peripheral bus for communicating with a host in accordance with a peripheral-bus specification that specifies a physical reset signal asserted by the host. The circuitry is configured to execute predefined logic that evaluates a reset condition that is indicative of imminent assertion of the physical reset signal by the host, and to perform a reset procedure in response to meeting the reset condition.

公开(公告)号：US20220021393A1

公开(公告)日：2022-01-20

申请号：US16920772

申请日：2020-07-06

Applicant: Mellanox Technologies, Ltd.

Inventor： Ran Ravid ,  Aviv Berg ,  Lavi Koch ,  Chen Gaist ,  Dotan David Levi

IPC: H03L7/08 ,  H03L7/099 ,  H04L7/033 ,  G06F1/12

Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.

公开(公告)号：US20220006606A1

公开(公告)日：2022-01-06

申请号：US17335122

申请日：2021-06-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ariel Shahar ,  Shahaf Shuler ,  Ariel Almog ,  Eitan Hirshberg ,  Natan Manevich

IPC: H04L7/00

Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.

公开(公告)号：US20210409137A1

公开(公告)日：2021-12-30

申请号：US16910193

申请日：2020-06-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Dotan David Levi ,  Ran Ravid ,  Guy Lederman

IPC: H04J3/06 ,  H04L29/06 ,  H04L12/46 ,  H04L12/26

Abstract: In certain exemplary embodiments, a switching device is provided, including an input interface configured to communicate with a packet source, an output interface configured to communicate with a packet destination, and packet processing circuitry. The packet processing circuitry is configured to receive a plurality of packets from the packet source via the input interface, each of the plurality of packets being associated with a packet descriptor, at least one of the packet descriptors being a transmission time packet descriptor including a desired physical transmission time for the packet associated with the transmission time packet descriptor, to receive an indication of a clock time, and for each packet associated with a transmission time packet descriptor, to physically transmit the packet associated with the transmission time packet descriptor, via the output interface, at a clock time corresponding to the desired physical transmission time. Related apparatus an methods are also provided.

公开(公告)号：US20210392065A1

公开(公告)日：2021-12-16

申请号：US16900931

申请日：2020-06-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Ran Sela ,  Liron Mula ,  Ran Ravid ,  Guy Lederman ,  Dotan David Levi

IPC: H04L12/26 ,  H04J3/06

Abstract: In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.

公开(公告)号：US20210385169A1

公开(公告)日：2021-12-09

申请号：US17409625

申请日：2021-08-23

Applicant: Mellanox Technologies Ltd.

Inventor： Avi Urman ,  Lior Narkis ,  Gil Kremer ,  Saar Tarnopolsky ,  Dotan David Levi

IPC: H04L12/823 ,  H04L29/06 ,  H04L12/707 ,  H04L12/815

Abstract: Apparatuses, systems, and techniques to eliminate redundant data packets. In at least one embodiment, a communication apparatus generates redundant data packets, and sends them in multiple packet streams. In at least one embodiment, a communication apparatus eliminates redundant data packets from received packet streams.