公开(公告)号：US12079513B2

公开(公告)日：2024-09-03

申请号：US17657870

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Paolo Amato ,  Daniele Balluchi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0679

Abstract: Methods, systems, and devices for log management maintenance operation and command are described. A method may include receiving, at a memory system, a command associated with maintenance for the memory system and indicating to initiate collecting values of a parameter, storing a value of the parameter, and transmitting, to a host system, a message indicating an availability of the value of the parameter based at least in part on storing the value of the parameter. An additional method may include transmitting, to a host system, a message indicating that a quantity of errors for an address of an address space associated with the memory system satisfies a threshold, receiving a command associated with maintenance for the memory system and indicating a retirement of the address, and retiring the address for the address space associated with the memory system based at least in part on receiving the command.

公开(公告)号：US20240070284A1

公开(公告)日：2024-02-29

申请号：US18237247

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Alessandro Orlando ,  Niccolò Izzo ,  Angelo Alberto Rovelli ,  Danilo Caraccio ,  Federica Cresci ,  Craig A. Jones

IPC: G06F21/57

CPC classification number: G06F21/575 ,  G06F21/572 ,  G06F2221/033

Abstract: Protection for a secure boot procedure can be provided in addition to cryptographic verification of boot firmware associated with the boot procedure. While the boot firmware is being verified, an open sub-system can be placed into a halt state, during which the open sub-system is prevented from performing the boot procedure. The open sub-system can be subsequently placed into a resume state to further perform the boot procedure when the boot firmware is verified. The open sub-system is still prevented from performing the boot procedure even if the boot firmware is verified unless the open sub-system is placed into the resume state again.

公开(公告)号：US20240070283A1

公开(公告)日：2024-02-29

申请号：US18237229

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Alessandro Orlando ,  Niccolò Izzo ,  Angelo Alberto Rovelli ,  Danilo Caraccio ,  Federica Cresci ,  Craig A. Jones

IPC: G06F21/57

CPC classification number: G06F21/575 ,  G06F21/572

Abstract: Protection for a secure boot procedure can be provided in addition to cryptographic verification of boot firmware associated with the boot procedure. While the boot firmware is being verified and executed at a secure sub-system, an open sub-system can be put into a halt state, during which the open sub-system is prevented from performing the boot procedure. The open sub-system is still prevented from performing the boot procedure even if the boot firmware is verified and/or executed unless the open sub-system is put into the resume state again.

公开(公告)号：US20240007265A1

公开(公告)日：2024-01-04

申请号：US18215479

申请日：2023-06-28

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Niccolò Izzo ,  Marco Sforzin

IPC: H04L9/06 ,  H04L9/32 ,  G06F21/64

CPC classification number: H04L9/0618 ,  H04L9/32 ,  G06F21/64

Abstract: A memory system can be provided with error detection capabilities at various levels and authentication and integrity check capabilities in parallel with data security schemes. The error detection capabilities can check for any errors not only on data paths within a memory controller, but also on data stored in memory devices. The authentication capabilities provided in parallel with the data security schemes can ensure/strengthen data integrity of the memory system to be compliant with standardized requirements and/or protocols, such as trusted execution engine security protocol (TSP).

公开(公告)号：US20230393770A1

公开(公告)日：2023-12-07

申请号：US17946518

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Sujeet Ayyapureddi ,  Edmund J. Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Robert M. Walker ,  Danilo Caraccio

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

公开(公告)号：US20230367663A1

公开(公告)日：2023-11-16

申请号：US18137895

申请日：2023-04-21

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Alessandro Orlando ,  Danilo Caraccio ,  Roberto Izzi

IPC: G06F11/07 ,  G06F11/30

CPC classification number: G06F11/073 ,  G06F11/0772 ,  G06F11/076 ,  G06F11/0781 ,  G06F11/3037

Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.

公开(公告)号：US20230297285A1

公开(公告)日：2023-09-21

申请号：US18121874

申请日：2023-03-15

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Anandhavel Nagendrakumar ,  Mohammed Ebrahim Hargan ,  Scott Garner ,  Danilo Caraccio ,  Daniele Balluchi ,  Chia Wei Chang ,  Ankush Lal

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G11C11/406

Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

公开(公告)号：US20230274002A1

公开(公告)日：2023-08-31

申请号：US17682928

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Alessandro Orlando ,  Niccolo' Izzo ,  Danilo Caraccio

IPC: G06F21/57 ,  H04L9/32

CPC classification number: G06F21/572 ,  H04L9/3263 ,  G06F2221/033 ,  G06F9/4406

Abstract: Disclosed in some examples are methods, systems, and devices for authenticating a firmware object on a device and in some examples to safeguard the attestation process from the execution of malicious firmware. In some examples, a firmware update process may, in addition to updating the firmware on the device, write a hash of the authentic firmware code in a secure storage device (e.g., a register). This may be done in some examples in a protected environment (e.g., a trusted execution environment or a protected firmware update process). Upon first boot after the update, a firmware update checker compares the firmware object that is booted with the value of the secure storage device. If the values match, the alias certificate may be regenerated, and the boot continues. If the values do not match, then the alias certificate may not be regenerated, and the system may have an authenticity failure because the key and the certificate do not match.

公开(公告)号：US11687273B2

公开(公告)日：2023-06-27

申请号：US17489336

申请日：2021-09-29

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Paolo Amato ,  Marco Sforzin ,  Danilo Caraccio ,  Daniele Balluchi

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0619 ,  G06F3/0679

Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can manage memory devices according to different protocols. For a first protocol, the memory device performs error correction operations and for a second protocol, the memory controller performs error correction operations. For the first protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data pins. For the second protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data mask inversion pins. The second protocol can have some features disabled that are enabled according to the first protocol, such as low-power features.

公开(公告)号：US20220197504A1

公开(公告)日：2022-06-23

申请号：US17692241

申请日：2022-03-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Francesco Falanga ,  Danilo Caraccio

IPC: G06F3/06 ,  G06F12/02

Abstract: Memory devices might include an array of memory cells, a register, and a controller for access of the array of memory cells. The controller might be configured to autonomously perform background operations on the array of memory cells in response to the register storing a first value, and prohibit autonomous performance of the background operations on the array of memory cells in response to the register storing a second value different than the first value. The memory devices might be in communication with a host.