公开(公告)号：US11775389B2

公开(公告)日：2023-10-03

申请号：US17690742

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to defer performance of an error-correction parity calculation for a block of a memory components of the memory subsystem. In particular, a memory sub-system controller of some embodiments can defer (e.g., delay) performance of an error-correction parity calculation and can defer the error-correction parity calculation such that it is performed at a time when the memory sub-system satisfies an idle state condition.

公开(公告)号：US20230305617A1

公开(公告)日：2023-09-28

申请号：US18096288

申请日：2023-01-12

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Christian M. Gyllenskog ,  Giuseppe Cariello ,  Marco Onorato ,  Roberto IZZI ,  Stephen Hanna ,  Jonathan S. Parry ,  Reshmi Basu ,  Nadav Grosz ,  David Aaron Palmer

IPC: G06F1/3234 ,  G06F9/4401 ,  G06F1/324

CPC classification number: G06F1/3275 ,  G06F1/324 ,  G06F9/4411

Abstract: Methods, systems, and devices for dynamic power modes for boot-up procedures are described. A memory system may initiate a boot-up procedure according to a predefined first power mode that is associated with a first power consumption. The memory system may then determine whether to perform the boot-up procedure according to the first power mode or a second power mode associated with a different second power consumption. In cases that the memory system receives an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the second power mode. Additionally, in cases that the memory system does not receive an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the first power mode.

公开(公告)号：US11762565B2

公开(公告)日：2023-09-19

申请号：US17701356

申请日：2022-03-22

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/068 ,  G06F3/0659

Abstract: Apparatus and methods are disclosed, including a controller circuit, a volatile memory, a non-volatile memory, and a reset circuit, where the reset circuit is configured to receive a reset signal from a host device and actuate a timer circuit. The timer circuit, where the timer circuit is configured to cause a storage device to reset after a threshold time period. The reset circuit is further configured to actuate the controller circuit to write data stored in the volatile memory to the non-volatile memory before the storage device is reset.

公开(公告)号：US11740963B2

公开(公告)日：2023-08-29

申请号：US17851782

申请日：2022-06-28

Applicant: Micron Technology, Inc.

Inventor： Jonathan Scott Parry ,  Nadav Grosz ,  David Aaron Palmer ,  Christian M. Gyllenskog

IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/1072 ,  G06F12/0246

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

公开(公告)号：US11740679B2

公开(公告)日：2023-08-29

申请号：US17014693

申请日：2020-09-08

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F1/32 ,  G06F1/3228 ,  G06F17/18 ,  G06F1/3296 ,  G06F1/3234

CPC classification number: G06F1/3228 ,  G06F1/3275 ,  G06F1/3296 ,  G06F17/18

Abstract: Devices and techniques are disclosed herein for predicting and optimizing energy usage of a device during low-power operation. In an example, a method can include storing a duration of a plurality of low-power intervals of a device, determining a probable duration of a next low-power interval of the device based on the durations of the plurality of low-power intervals, determining a low-power state of the device for the next low-power interval based on the probable duration, upon initiating the next low-power interval, saving state information of one or more sub-systems of the device to provide first state information in response to the low-power state, and upon initiating the next low-power interval, reducing a power state of the one or more sub-systems.

公开(公告)号：US11714712B2

公开(公告)日：2023-08-01

申请号：US17872462

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F11/10 ,  G11C29/52 ,  G06F12/10 ,  H03M13/29

CPC classification number: G06F11/1068 ,  G06F12/10 ,  G11C29/52 ,  H03M13/2906 ,  G06F2212/1044

Abstract: Devices and techniques for extended error correction in a storage device are described herein. A first set of data, that has a corresponding logical address and physical address, is received. A second set of data can be selected based on the logical address. Secondary error correction data can be computed from the first set of data and the second set of data. Primary error correction data can be differentiated from the secondary error correction data by being computed from the first set of data and a third set of data. The third set of data can be selected based on the physical address of the first set of data. The secondary error correction data can be written to the storage device based on the logical address.

公开(公告)号：US20230185713A1

公开(公告)日：2023-06-15

申请号：US17968607

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/02 ,  G06F12/0891

CPC classification number: G06F12/0292 ,  G06F12/0891 ,  G06F12/0253

Abstract: Methods, systems, and devices for valid data identification for garbage collection are described. In connection with writing data to a block of memory cells, a memory system may identify a portion of a logical address space that includes a logical address for the data. The memory system may set a bit of a bitmap, which may indicate that the block includes data having a logical address within a portion of the logical address space corresponding to the bit. The logical address space may be divided into any quantity of portions, each corresponding to a different subset of a logical-to-physical (L2P) table, and the bitmap may include any quantity of corresponding bits. To perform garbage collection on the block, the bitmap may be used to identify one or more subsets of the L2P table to evaluate to determine whether different sets of data within the block are valid or invalid.

公开(公告)号：US11625323B2

公开(公告)日：2023-04-11

申请号：US17113999

申请日：2020-12-07

Applicant: Micron Technology, Inc.

Inventor： Sharath Chandra Ambula ,  Sushil Kumar ,  David Aaron Palmer ,  Venkata Kiran Kumar Matturi ,  Sri Ramya Pinisetty

IPC: G06F12/02 ,  G06F12/0831

Abstract: Methods, systems, and devices for session-based memory operation are described. A memory system may determine that a logical address targeted by a read command is associated with a session table. The memory system may write the session table to a cache based on the logical address being associated with the session table. After writing the session table to the cache, the memory system may use the session table to determine one or more logical-to-physical (L2P) tables and write the one or more L2P tables to the cache. The memory system may use the L2L tables to perform address translation for logical addresses.

公开(公告)号：US20230049678A1

公开(公告)日：2023-02-16

申请号：US17399771

申请日：2021-08-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Aaron Palmer

IPC: G06F3/06

Abstract: Methods, systems, and devices for adjusting a granularity associated with read disturb tracking are described. In some examples, a memory system may receive a set of read commands from a host system instructing the memory system to read data stored at a memory array. The memory system may track a quantity of executed read commands corresponding to a first portion of the memory array according to a first granularity and determine whether the quantity of read commands satisfies a threshold. If the quantity of read commands satisfies the threshold, the memory system may adjust the granularity for tracking executed read commands for the first portion from the first granularity to a second granularity. For example, the memory system may increase or decrease the granularity for tracking executed read commands for the first portion. The memory system may use the tracked quantities of executed read commands for read disturb remediation.

公开(公告)号：US20230040336A1

公开(公告)日：2023-02-09

申请号：US17396117

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  David Aaron Palmer ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/08

Abstract: Methods, systems, and devices for adaptive throughput monitoring are described. In some examples, a memory system may be associated with one or more clocks that are each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system may determine a throughput of the commands. Based on the determined throughput, the memory system may adjust a rate of one or more of the clocks.