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公开(公告)号：US20200321053A1
公开(公告)日：2020-10-08
申请号：US16905104
申请日：2020-06-18
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Riccardo Muzzetto , Umberto Di Vincenzo
Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.
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公开(公告)号：US10726917B1
公开(公告)日：2020-07-28
申请号：US16254962
申请日：2019-01-23
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Riccardo Muzzetto , Umberto Di Vincenzo
Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.
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公开(公告)号：US20200234761A1
公开(公告)日：2020-07-23
申请号：US16254962
申请日：2019-01-23
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Riccardo Muzzetto , Umberto Di Vincenzo
Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.
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公开(公告)号：US20190013058A1
公开(公告)日：2019-01-10
申请号：US15641783
申请日：2017-07-05
Applicant: Micron Technology, Inc.
Inventor： Riccardo Muzzetto
Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.
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公开(公告)号：US20150092470A1
公开(公告)日：2015-04-02
申请号：US14041585
申请日：2013-09-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Daniele Vimercati , Riccardo Muzzetto
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/02 , G11C7/04 , G11C7/14 , G11C13/0004 , G11C2013/0045 , G11C2013/0054
Abstract: This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory device, can determine a value of a data digit, such as a bit, stored in a non-volatile memory cell based at least partly on the reference current. The reference current can be generated by mirroring a current at a node that is biased by a voltage bias. A configurable resistance circuit can have a resistance that is configurable. The resistance of the configurable resistance circuit can be in series between the node and a resistive non-volatile memory element. In some embodiments, a plurality of non-volatile memory elements can each be electrically connected in series between the resistance of the configurable resistance circuit and a corresponding selector.
Abstract translation: 本公开涉及生成用于存储器件的参考电流。 在一个方面，诸如相变存储器件的非易失性存储器件可以至少部分地基于参考电流来确定存储在非易失性存储器单元中的诸如位之类的数据位的值。 参考电流可以通过在由电压偏置偏置的节点处的电流进行镜像来产生。 可配置的电阻电路可以具有可配置的电阻。 可配置电阻电路的电阻可以串联在节点和电阻性非易失性存储器元件之间。 在一些实施例中，多个非易失性存储器元件可以各自在可配置电阻电路的电阻和相应的选择器之间串联电连接。
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Patent Agency Ranking
公开(公告)号：US12183380B2
公开(公告)日：2024-12-31
申请号：US17362348
申请日：2021-06-29
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Umberto Di Vincenzo , Riccardo Muzzetto , Angelo Visconti
Abstract: Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After receiving a read command, the memory device may couple each capacitive circuit with a respective memory cell (e.g., to transfer a charge stored by each respective memory cell to a capacitive circuit) and may couple the second capacitor of each capacitive circuit to a reference voltage bus. Thus, a reference voltage on the reference voltage bus may be based on an average charge across the second capacitors of each capacitive circuit. The memory device may then compare a charge stored by the first and second capacitors of each capacitive circuit with the reference voltage bus and may output a set of values stored by the set of memory cells based on the comparing.
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公开(公告)号：US20240395297A1
公开(公告)日：2024-11-28
申请号：US18750750
申请日：2024-06-21
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Riccardo Muzzetto , Umberto di Vincenzo
Abstract: A method for accessing of memory cells where a set of user data is stored in a plurality of memory cells of the memory array, including: latching a current row address of a selected plurality of memory access; comparing a last row address with the current row address; if the result of the comparison is negative, executing a leakage compensation algorithm through a memory sensing circuitry; if the result of the comparison is positive, waiting for the completion of a write to read procedure on the selected plurality of memory cells.
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公开(公告)号：US12051463B2
公开(公告)日：2024-07-30
申请号：US17864004
申请日：2022-07-13
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Jeffrey E. Koelling , Hari Giduturi , Riccardo Muzzetto , Corrado Villa
IPC: G11C13/00
CPC classification number: G11C13/0026 , G11C13/0004 , G11C13/0028 , G11C13/003 , G11C13/0033
Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.
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公开(公告)号：US12027230B2
公开(公告)日：2024-07-02
申请号：US17498919
申请日：2021-10-12
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Riccardo Muzzetto , Umberto di Vincenzo
CPC classification number: G11C7/222 , G11C7/1039 , G11C7/1069 , G11C7/1096 , G11C8/18 , G11C16/3404
Abstract: A method for accessing of memory cells where a set of user data is stored in a plurality of memory cells of the memory array, including: latching a current row address of a selected plurality of memory access; comparing a last row address with the current row address; if the result of the comparison is negative, executing a leakage compensation algorithm through a memory sensing circuitry; if the result of the comparison is positive, waiting for the completion of a write to read procedure on the selected plurality of memory cells.
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公开(公告)号：US11963370B2
公开(公告)日：2024-04-16
申请号：US17043392
申请日：2020-03-03
Applicant: Micron Technology, Inc.
Inventor： Riccardo Muzzetto , Ferdinando Bedeschi , Umberto di Vincenzo
CPC classification number: H10B63/84 , G11C13/0004 , G11C13/003 , H10N70/231 , G11C2213/71
Abstract: The present disclosure relates to a memory device comprising an array of memory cells arranged in a multideck configuration comprising a plurality of superimposed decks, a plurality of access lines comprising at least a first plurality of access lines arranged in a first level, a second plurality of access lines arranged in a second level, and a third plurality of access lines arranged in a third level between the first plurality of access lines and the second plurality of access lines, the third plurality of access lines being arranged between two decks of the plurality of decks, a plurality of drivers configured to drive signals to the access lines, and connection elements configured to electrically connect the access lines to the respective drivers. The connections elements and the access lines are arranged so that a single driver of the plurality of drivers is configured to drive at least one access line of each level of the at least three levels. Related memory systems and methods are also disclosed.
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