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    FAST DETECTION OF DEFECTIVE MEMORY BLOCK TO PREVENT NEIGHBOR PLANE DISTURB
    101.
    发明申请
    FAST DETECTION OF DEFECTIVE MEMORY BLOCK TO PREVENT NEIGHBOR PLANE DISTURB 审中-公开

    公开(公告)号：US20190214100A1

    公开(公告)日：2019-07-11

    申请号：US15863404

    申请日：2018-01-05

    Applicant: SanDisk Technologies LLC

    Inventor： Sarath Puthenthermadam ,  Deepanshu Dutta ,  Long Pham

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/32

    Abstract: A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.

    WRITE ABORT DETECTION FOR MULTI-STATE MEMORIES
    105.
    发明申请
    WRITE ABORT DETECTION FOR MULTI-STATE MEMORIES 审中-公开

    公开(公告)号：US20170243638A1

    公开(公告)日：2017-08-24

    申请号：US15588968

    申请日：2017-05-08

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Cynthia Hua-Ling Hsu ,  Aaron Lee ,  Abhijeet Manohar ,  Deepanshu Dutta

    IPC: G11C11/56

    CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/3459

    Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

    XOR DATA RECOVERY SCHEMES NONVOLATILE MEMORY DEVICES
    107.
    发明公开
    XOR DATA RECOVERY SCHEMES NONVOLATILE MEMORY DEVICES 审中-公开

    公开(公告)号：US20240347122A1

    公开(公告)日：2024-10-17

    申请号：US18754911

    申请日：2024-06-26

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Deepanshu Dutta ,  Luca Fasoli

    IPC: G11C29/10 ,  G06F11/10

    CPC classification number: G11C29/10 ,  G06F11/1044

    Abstract: A memory package includes a plurality of memory dies, each of which has a plurality of memory blocks with arrays of memory cells. The memory dies include user data dies that contain user data and an XOR die that contains XOR data. The memory package also includes circuitry for reading the user data and the XOR data. The circuitry is configured to detect a read error during a read operation in a failed die of the plurality of user data dies and read some of the user data of the user data dies besides the failed die and reading some of the XOR data of the XOR die. The circuitry is also configured to perform a read recovery operation that includes an XOR operation using, as inputs, the user data of the user data dies besides the failed die and the XOR data of the XOR die.

    OPEN BLOCK READ ICC REDUCTION
    109.
    发明公开
    OPEN BLOCK READ ICC REDUCTION 审中-公开

    公开(公告)号：US20240290395A1

    公开(公告)日：2024-08-29

    申请号：US18360634

    申请日：2023-07-27

    Applicant: SanDisk Technologies LLC

    Inventor： Abu Naser Zainuddin ,  Jiahui Yuan ,  Deepanshu Dutta

    IPC: G11C16/28 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

    CPC classification number: G11C16/28 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24

    Abstract: Technology is disclosed herein for a storage system that reduces the Icc during open block reads. A lower than nominal voltage may be applied to the bit lines during open block reads, which reduces Icc. A nominal bit line voltage may be used during closed block reads. The lower than nominal bit line voltage may be combined with using a lower than nominal read pass voltage (Vread) to unprogrammed word lines during the open block read. The lower than nominal Vread has a lower magnitude than a nominal Vread used during a closed block read. Combining the lower than nominal bit line voltage with the lower than nominal Vread to unprogrammed word lines further reduces Icc during open block reads. The ramp rate of Vread may be relaxed (made slower) during at least some open block reads in combination with the lower than nominal bit line voltage.

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