公开(公告)号：US20050282296A1

公开(公告)日：2005-12-22

申请号：US10873326

申请日：2004-06-21

申请人： Sheng Hsu ,  Tingkai Li

发明人： Sheng Hsu ,  Tingkai Li

IPC分类号： H01L21/00 ,  H01L29/78

CPC分类号： H01L29/78391

摘要： A method of fabricating and programming a ferroelectric memory transistor for asymmetrical programming includes fabricating a ferroelectric memory transistor having a metal oxide layer overlaying a gate region; and programming the ferroelectric memory transistor so that a low threshold voltage is about equal to the intrinsic threshold voltage of the ferrorelectric memory transistor.

摘要翻译： 制造和编程用于非对称编程的铁电存储晶体管的方法包括制造具有覆盖栅极区域的金属氧化物层的铁电存储晶体管; 并且对铁电存储晶体管进行编程，使得低阈值电压约等于铁电介质存储晶体管的固有阈值电压。

公开(公告)号：US20050207265A1

公开(公告)日：2005-09-22

申请号：US11130983

申请日：2005-05-16

申请人： Sheng Hsu ,  Tingkai Li ,  David Evans ,  Wei-Wei Zhuang ,  Wei Pan

发明人： Sheng Hsu ,  Tingkai Li ,  David Evans ,  Wei-Wei Zhuang ,  Wei Pan

IPC分类号： H01L27/10 ,  G11C11/15 ,  G11C13/00 ,  H01L45/00 ,  G11C8/02

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1625

摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.

摘要翻译： 提供了非对称结构的存储单元和制造方法。 该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。 在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度 的第一层。 在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

公开(公告)号：US20050207248A1

公开(公告)日：2005-09-22

申请号：US11130981

申请日：2005-05-16

申请人： Sheng Hsu

发明人： Sheng Hsu

IPC分类号： G11C7/00 ,  G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24

CPC分类号： G11C13/0007 ,  G11C11/15 ,  G11C11/5685 ,  G11C2213/31 ,  G11C2213/72 ,  H01L27/24

摘要： A shared bit line cross-point memory array structure is provided, along with methods of manufacture. The memory structure comprises a bottom word line with a top word line overlying the bottom word line. A bit line is interposed between the bottom word line and the top word line such that a first cross-point is formed between the bottom word line and the bit line and a second cross-point is formed between the bit line and the top word line. A resistive memory material is provided at each cross-point above and below the bit line. A diode is formed at each cross-point between the resistive memory material and either the top word line or the bottom word line, respectively.

摘要翻译： 提供共享位线交叉点存储器阵列结构以及制造方法。 存储器结构包括具有覆盖底部字线的顶部字线的底部字线。 位线位于底部字线和顶部字线之间，使得在底部字线和位线之间形成第一交叉点，并且在位线和顶部字线之间形成第二交叉点 。 在位线上方和下方的每个交叉点处提供电阻式存储器材料。 在电阻性存储器材料和顶部字线或底部字线之间的每个交叉点分别形成二极管。

公开(公告)号：US20050158994A1

公开(公告)日：2005-07-21

申请号：US10759468

申请日：2004-01-15

申请人： Wei-Wei Zhuang ,  Lisa Stecker ,  Gregory Stecker ,  Sheng Hsu

发明人： Wei-Wei Zhuang ,  Lisa Stecker ,  Gregory Stecker ,  Sheng Hsu

IPC分类号： C01G45/00 ,  H01L21/28 ,  H01L23/62 ,  H01L27/10 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1683

摘要： A Pr1-XCaXMnO3 (PCMO) spin-coat deposition method for eliminating voids is provided, along with a void-free PCMO film structure. The method comprises: forming a substrate, including a noble metal, with a surface; forming a feature, such as a via or trench, normal with respect to the substrate surface; spin-coating the substrate with acetic acid; spin-coating the substrate with a first, low concentration of PCMO solution; spin-coating the substrate with a second concentration of PCMO solution, having a greater concentration of PCMO than the first concentration; baking and RTA annealing (repeated one to five times); post-annealing; and, forming a PCMO film with a void-free interface between the PCMO film and the underlying substrate surface. The first concentration of PCMO solution has a PCMO concentration in the range of 0.01 to 0.1 moles (M). The second concentration of PCMO solution has a PCMO concentration in the range of 0.2 to 0.5 M.

摘要翻译： 提供了一种用于消除空隙的Pr 1-X C 3 Mn 3 O 3（PCMO）旋涂沉积方法，以及无空隙 PCMO薄膜结构。 该方法包括：用表面形成包括贵金属的基底; 形成相对于衬底表面正常的特征，例如通孔或沟槽; 用乙酸旋涂底物; 用第一种低浓度的PCMO溶液旋涂底物; 以第二浓度的PCMO溶液旋涂底物，其具有比第一浓度更高浓度的PCMO; 烘烤和RTA退火（重复1〜5次）; 后退火; 并且在PCMO膜和下面的衬底表面之间形成具有无空隙界面的PCMO膜。 PCMO溶液的第一浓度的PCMO浓度范围为0.01至0.1摩尔（M）。 PCMO溶液的第二浓度的PCMO浓度范围为0.2-0.5M。

公开(公告)号：US20050110117A1

公开(公告)日：2005-05-26

申请号：US10720890

申请日：2003-11-24

申请人： Sheng Hsu

发明人： Sheng Hsu

IPC分类号： H01L21/8247 ,  G11C11/15 ,  G11C13/00 ,  H01L27/10 ,  H01L27/115 ,  H01L27/24 ,  H01L43/08 ,  H01L29/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/101 ,  H01L27/24

摘要： A memory array layer for use in a 3D RRAM is formed, with peripheral circuitry, on a silicon substrate; layers of silicon oxide, bottom electrode material, silicon oxide, resistor material, silicon oxide, silicon nitride, silicon oxide, top electrode and covering oxide are deposited and formed. Multiple memory array layers may be formed on top of one another. The RRAM of the invention may be programmed in a single step or a two step programming process.

摘要翻译： 在硅衬底上形成用于3D RRAM的存储器阵列层，具有外围电路; 沉积和形成氧化硅，底部电极材料，氧化硅，电阻材料，氧化硅，氮化硅，氧化硅，顶部电极和覆盖氧化物的层。 多个存储器阵列层可以形成在彼此之上。 本发明的RRAM可以在单个步骤或两步编程过程中进行编程。

公开(公告)号：US20050054138A1

公开(公告)日：2005-03-10

申请号：US10971263

申请日：2004-10-21

申请人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24 ,  H01L21/00

CPC分类号： G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/24

摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

公开(公告)号：US20050037520A1

公开(公告)日：2005-02-17

申请号：US10640770

申请日：2003-08-13

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  David Evans ,  Sheng Hsu ,  Wei Pan

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  David Evans ,  Sheng Hsu ,  Wei Pan

IPC分类号： H01L27/04 ,  H01L21/20 ,  H01L21/822 ,  H01L45/00 ,  H01L21/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.

摘要翻译： 当与高度结晶的种子层集成时，用于获得PCMO薄膜上的可逆电阻开关的方法包括通过MOCVD沉积高度结晶形式的PCMO的种子层，薄膜的厚度为约50埃至300埃 通过旋转涂覆沉积种子层上的第二PCMO薄膜层，其厚度为约500埃至3000埃以形成组合的PCMO层; 通过施加约-4V至-5V之间的脉冲宽度在约75ns至1个音箱之间的负电脉冲来增加半导体器件中组合的PCMO膜的电阻; 并且通过施加脉冲宽度大于2.0个音箱的约+ 2.5V至+ 4V之间的正电脉冲来降低半导体器件中组合的PCMO层的电阻。

公开(公告)号：US20080090317A1

公开(公告)日：2008-04-17

申请号：US11998341

申请日：2007-11-29

申请人： Sheng Hsu ,  Tingkai Li ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Tingkai Li ,  Wei-Wei Zhuang

IPC分类号： H01L33/00

CPC分类号： H01L33/08 ,  B82Y20/00 ,  H01L33/18 ,  H01L33/24 ,  H01L33/34 ,  H01L33/502 ,  Y10S977/834

摘要： A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.

摘要翻译： 提供了一种纳米末端电致发光（EL）二极管和一种用于制造所述器件的方法。 该方法包括：形成多个Si纳米二极管; 形成覆盖所述纳米二极管的磷光体层; 并且形成覆盖磷光体层的顶部电极。 纳米二极管通过以下方式形成：形成具有顶表面的Si衬底; 形成Si对孔; 形成层叠Si层的厚度为30〜300纳米（nm）的Si的n +层; 形成覆盖在衬底顶表面上的反应离子蚀刻（RIE）诱导的聚合物草; 使用RIE诱导的聚合物草作为掩模，蚀刻未被掩模覆盖的基底的区域; 以及在由掩模覆盖的衬底的区域中形成纳米二极管二极管。

公开(公告)号：US20070238246A1

公开(公告)日：2007-10-11

申请号：US11403020

申请日：2006-04-11

申请人： Tingkai Li ,  Sheng Hsu ,  David Evans

发明人： Tingkai Li ,  Sheng Hsu ,  David Evans

IPC分类号： H01L21/336

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1641

摘要： A method of fabricating a RRAM includes preparing a substrate and forming a bottom electrode ori the substrate. A PCMO layer is deposited on the bottom electrode using MOCVD or liquid MOCVD, followed by a post-annealing process. The deposited PCMO thin film has a crystallized PCMO structure or a nano-size and amorphous PCMO structure. A top electrode is formed on the PCMO layer.

摘要翻译： 制造RRAM的方法包括制备衬底并形成底部电极或衬底。 使用MOCVD或液体MOCVD将PCMO层沉积在底部电极上，随后进行后退火处理。 沉积的PCMO薄膜具有结晶的PCMO结构或纳米尺寸和无定形PCMO结构。 顶部电极形成在PCMO层上。

公开(公告)号：US20070238203A1

公开(公告)日：2007-10-11

申请号：US11403022

申请日：2006-04-11

申请人： Wei-Wei Zhuang ,  David Evans ,  Tingkai Li ,  Sheng Hsu

发明人： Wei-Wei Zhuang ,  David Evans ,  Tingkai Li ,  Sheng Hsu

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L21/31691 ,  H01L22/14

摘要： A method of monitoring synthesis of PCMO precursor solutions includes preparing a PCMO precursor solution and withdrawing samples of the precursor solution at intervals during a reaction phase of the PCMO precursor solution synthesis. The samples of the PCMO precursor solution are analyzed by UV spectroscopy to determine UV transmissivity of the samples of the PCMO precursor solution and the samples used to form PCMO thin films. Electrical characteristics of the PCMO thin films formed from the samples are determined to identify PCMO thin films having optimal electrical characteristics. The UV spectral characteristics of the PCMO precursor solutions are correlated with the PCMO thin films having optimal electrical characteristics. The UV spectral characteristics are used to monitor synthesis of future batches of the PCMO precursor solutions, which will result in PCMO thin films having optimal electrical characteristics.

摘要翻译： 监测PCMO前体溶液合成的方法包括制备PCMO前体溶液，并在PCMO前体溶液合成反应期间间隔取出前体溶液样品。 通过紫外光谱分析PCMO前体溶液的样品，以确定PCMO前体溶液和用于形成PCMO薄膜的样品的UV透射率。 确定由样品形成的PCMO薄膜的电特性以鉴定具有最佳电特性的PCMO薄膜。 PCMO前体溶液的UV光谱特性与具有最佳电学特性的PCMO薄膜相关。 UV光谱特性用于监测未来批次的PCMO前体溶液的合成，这将导致具有最佳电特性的PCMO薄膜。