公开(公告)号：US20080026590A1

公开(公告)日：2008-01-31

申请号：US11494141

申请日：2006-07-26

申请人： Wei-Wei Zhuang ,  Yoshi Ono ,  Tingkai Li

发明人： Wei-Wei Zhuang ,  Yoshi Ono ,  Tingkai Li

IPC分类号： H01L21/31

CPC分类号： C23C18/1295 ,  C23C18/1208 ,  C23C18/1279 ,  C23C18/1283

摘要： A method of making a doped silicon oxide thin film using a doped silicon oxide precursor solution includes mixing a silicon source in an organic acid and adding 2-methoxyethyl ether to the silicon source and organic acid to from a preliminary precursor solution. The resultant solution is heated, stirred and filtered. A doping impurity is dissolved in 2-methoxyethanol to from a doped source solution, and the resultant solution mixed with the previously described resultant solution to from a doped silicon oxide precursor solution. A doped silicon oxide thin film if formed on a wafer by spin coating. The thin film and the wafer are baked at progressively increasing temperatures and the thin film and the wafer are annealed.

摘要翻译： 使用掺杂的氧化硅前体溶液制造掺杂的氧化硅薄膜的方法包括将有机酸中的硅源混合并向硅源和有机酸中加入2-甲氧基乙醚至初始前体溶液。 将所得溶液加热，搅拌并过滤。 将掺杂杂质从掺杂的源溶液中溶解在2-甲氧基乙醇中，并将所得溶液与先前所述的溶液混合从掺杂的氧化硅前体溶液中。 如果通过旋涂在晶片上形成掺杂的氧化硅薄膜。 在逐渐升高的温度下烘烤薄膜和晶片，并对薄膜和晶片进行退火。

公开(公告)号：US20070238203A1

公开(公告)日：2007-10-11

申请号：US11403022

申请日：2006-04-11

申请人： Wei-Wei Zhuang ,  David Evans ,  Tingkai Li ,  Sheng Hsu

发明人： Wei-Wei Zhuang ,  David Evans ,  Tingkai Li ,  Sheng Hsu

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L21/31691 ,  H01L22/14

摘要： A method of monitoring synthesis of PCMO precursor solutions includes preparing a PCMO precursor solution and withdrawing samples of the precursor solution at intervals during a reaction phase of the PCMO precursor solution synthesis. The samples of the PCMO precursor solution are analyzed by UV spectroscopy to determine UV transmissivity of the samples of the PCMO precursor solution and the samples used to form PCMO thin films. Electrical characteristics of the PCMO thin films formed from the samples are determined to identify PCMO thin films having optimal electrical characteristics. The UV spectral characteristics of the PCMO precursor solutions are correlated with the PCMO thin films having optimal electrical characteristics. The UV spectral characteristics are used to monitor synthesis of future batches of the PCMO precursor solutions, which will result in PCMO thin films having optimal electrical characteristics.

摘要翻译： 监测PCMO前体溶液合成的方法包括制备PCMO前体溶液，并在PCMO前体溶液合成反应期间间隔取出前体溶液样品。 通过紫外光谱分析PCMO前体溶液的样品，以确定PCMO前体溶液和用于形成PCMO薄膜的样品的UV透射率。 确定由样品形成的PCMO薄膜的电特性以鉴定具有最佳电特性的PCMO薄膜。 PCMO前体溶液的UV光谱特性与具有最佳电学特性的PCMO薄膜相关。 UV光谱特性用于监测未来批次的PCMO前体溶液的合成，这将导致具有最佳电特性的PCMO薄膜。

公开(公告)号：US20050275064A1

公开(公告)日：2005-12-15

申请号：US10855942

申请日：2004-05-27

申请人： Tingkai Li ,  Lawrence Charneski ,  Wei-Wei Zhuang ,  David Evans ,  Sheng Hsu

发明人： Tingkai Li ,  Lawrence Charneski ,  Wei-Wei Zhuang ,  David Evans ,  Sheng Hsu

IPC分类号： H01L27/04 ,  H01L21/205 ,  H01L21/822 ,  H01L27/10 ,  H01L29/06 ,  H01L29/739 ,  H01L45/00

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1616

摘要： A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and, forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.

摘要翻译： 提供了多层Pr 1 x 1 x x MnO 3（PCMO）薄膜电容器和相关的沉积方法，用于形成双极开关 薄膜。 该方法包括：形成底部电极; 沉积纳米晶体PCMO层; 沉积多晶PCMO层; 形成具有双极开关特性的多层PCMO膜; 并且形成覆盖PCMO膜的顶部电极。 如果多晶层沉积在纳米晶层之上，则可以用窄脉冲宽度，负电压脉冲写入高电阻。 PCMO膜可以使用窄脉冲宽度，正幅度脉冲复位为低电阻。 同样，如果纳米晶层沉积在多晶层上，则可以用窄脉冲宽度，正电压脉冲写入高电阻，并使用窄脉冲宽度，负幅度脉冲将其复位为低电阻。

公开(公告)号：US20050054138A1

公开(公告)日：2005-03-10

申请号：US10971263

申请日：2004-10-21

申请人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24 ,  H01L21/00

CPC分类号： G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/24

摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

公开(公告)号：US20050136602A1

公开(公告)日：2005-06-23

申请号：US11039536

申请日：2005-01-19

申请人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： H01L21/76 ,  G11C13/00 ,  H01L21/3205 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L43/08 ,  H01L29/02 ,  H01L21/336 ,  H01L21/4763 ,  H01L47/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/101 ,  H01L27/24

摘要： A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si layer overlying the p-Si substrate; prior to forming the n+ Si bit lines, forming a p+ Si layer overlying the n+ Si layer; forming a layer of silicon nitride overlying the p+ layer; forming a top oxide layer overlying the silicon nitride layer; performing a first selective etch of the top oxide layer, the silicon nitride layer, the p+ Si layer, and a portion of the n+ Si layer, to form n+ Si bit lines and bit line trenches between the bit lines; forming an array of metal bottom electrodes overlying a plurality of n-doped silicon (n+ Si) bit lines, with intervening p-doped (p+) Si areas; forming a plurality of word line oxide isolation structures orthogonal to and overlying the n+ Si bit lines, adjacent to the bottom electrodes, and separating the p+ Si areas; forming a plurality of top electrode word lines, orthogonal to the n+ Si bit lines, with an interposing memory resistor material overlying the bottom electrodes; and, forming oxide-filled word line trenches adjacent the word lines.

摘要翻译： 已经提供了存储器阵列双沟槽隔离结构及其形成方法。 该方法包括：形成p掺杂硅（p-Si）衬底; 形成覆盖p-Si衬底的n掺杂（n +）Si层; 在形成n + Si位线之前，形成覆盖n + Si层的p + Si层; 形成覆盖p +层的氮化硅层; 形成覆盖所述氮化硅层的顶部氧化物层; 执行顶部氧化物层，氮化硅层，p + Si层和n + Si层的一部分的第一选择性蚀刻，以在位线之间形成n + Si位线和位线沟槽; 形成覆盖多个n掺杂硅（n + Si）位线的金属底部电极阵列，具有中间p掺杂（p +）Si区域; 形成与所述n + Si位线正交并覆盖与所述底部电极相邻并分离所述p + Si区域的多个字线氧化物隔离结构; 形成与n + Si位线正交的多个顶部电极字线，覆盖在底部电极上的插入式存储电阻材料; 并且在字线附近形成氧化物填充的字线沟槽。

公开(公告)号：US20050083757A1

公开(公告)日：2005-04-21

申请号：US10971204

申请日：2004-10-21

申请人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24 ,  G11C7/00

CPC分类号： G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  H01L27/24

摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

摘要翻译： 提供了电阻式交叉点存储器件，以及制造和使用方法。 存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。 在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 在电阻性存储器材料和下电极之间的界面处形成二极管，其可以形成为掺杂区域。 电阻交叉点存储器件通过在衬底内掺杂一行极性形成，然后将相反极性的线的掺杂区域形成二极管。 然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。 然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

公开(公告)号：US20050052942A1

公开(公告)日：2005-03-10

申请号：US10971203

申请日：2004-10-21

申请人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24 ,  G11C8/02

CPC分类号： G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/24

摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

公开(公告)号：US20070259127A1

公开(公告)日：2007-11-08

申请号：US11416986

申请日：2006-05-02

申请人： Yoshi Ono ,  Bruce Ulrich ,  Wei-Wei Zhuang ,  Douglas Tweet

发明人： Yoshi Ono ,  Bruce Ulrich ,  Wei-Wei Zhuang ,  Douglas Tweet

IPC分类号： B05D5/06 ,  B05D3/12 ,  B05D3/02 ,  H05H1/00

CPC分类号： G02B3/0012 ,  H01L27/14627

摘要： A method for densifying sol-gel films to form microlens structures includes preparing a sol-gel precursor, having at least one solvent therein. The sol-gel precursor is spin coated onto a wafer to form a sol-gel film thereon. The wafer and sol-gel film are hot plate baked at a temperature less than 200° C. to remove at least some of the solvent. The baked, wafer and spin-coated sol-gel film are treated with an oxygen plasma treatment to remove any remaining solvent and to densify the sol-gel film. The spin coating, hot plate baking and treating steps may be repeated as required. A microlens is formed from the densified sol-gel film.

摘要翻译： 用于致密化溶胶 - 凝胶膜以形成微透镜结构的方法包括制备其中具有至少一种溶剂的溶胶 - 凝胶前体。 将溶胶 - 凝胶前体旋涂在晶片上以在其上形成溶胶 - 凝胶膜。 将晶片和溶胶 - 凝胶膜在低于200℃的温度下进行热板烘烤以除去至少一些溶剂。 用氧等离子体处理烘烤，晶片和旋涂溶胶 - 凝胶膜以除去任何残留的溶剂并致密化溶胶 - 凝胶膜。 可以根据需要重复旋涂，热板烘烤和处理步骤。 从致密化的溶胶 - 凝胶膜形成微透镜。

公开(公告)号：US20060046204A1

公开(公告)日：2006-03-02

申请号：US10931596

申请日：2004-08-31

申请人： Yoshi Ono ,  Wei-Wei Zhuang ,  Wei Gao ,  Bruce Ulrich

发明人： Yoshi Ono ,  Wei-Wei Zhuang ,  Wei Gao ,  Bruce Ulrich

IPC分类号： G02B3/00

CPC分类号： G02B3/0012

摘要： A method of forming a microlens structure using a patternable lens material is provided. An organic-inorganic hybrid polymer comprising titanium dioxide is exposed to light using a defocused mask image and then developed to produce a lens-shaped region.

摘要翻译： 提供了使用可图案的透镜材料形成微透镜结构的方法。 使用散焦的掩模图像将包含二氧化钛的有机 - 无机杂化聚合物暴露于光，然后显影以产生透镜形区域。

公开(公告)号：US20050141269A1

公开(公告)日：2005-06-30

申请号：US11066708

申请日：2005-02-24

申请人： Sheng Hsu ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L27/115 ,  G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L43/08 ,  G11C11/00

CPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

摘要翻译： 提供了电阻式交叉点存储器件以及制造和使用方法。 存储器件包括插在上电极和下电极之间的钙钛矿材料的有源层。 在上电极和下电极的交叉点处位于有源层内的位区域具有响应于施加一个或更多个电压脉冲而可以在值范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 提供存储器电路以帮助编程和读出位区域。