公开(公告)号：US08102702B2

公开(公告)日：2012-01-24

申请号：US12545294

申请日：2009-08-21

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092

Abstract: An operation method of phase change memory (PCM) is provided. The operation method includes applying a RESET pulse to a phase change material of the PCM, wherein the RESET pulse has a profile with a first tail such that a plurality of seeds are formed in the phase change material. Due to the design of the RESET pulse in the operation method, it can speed up the crystal process.

Abstract translation: 提供了相变存储器（PCM）的操作方法。 该操作方法包括将RESET脉冲施加到PCM的相变材料，其中RESET脉冲具有带有第一尾部的轮廓，使得在相变材料中形成多个种子。 由于操作方法中RESET脉冲的设计，可以加快晶体过程。

公开(公告)号：US08102001B2

公开(公告)日：2012-01-24

申请号：US12891474

申请日：2010-09-27

Applicant: Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

Inventor： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

IPC: H01L23/62

CPC classification number: H01L23/62 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract translation: 一种用于静电放电（ESD）保护的半导体器件包括可控硅整流器（SCR），其包括半导体衬底，形成在衬底中的第一阱，形成在衬底中的第二阱，形成在第一阱中的第一p型区 用作阳极，以及部分地形成在第二阱中用作阴极的第一n型区域，形成在包括栅极的第一阱中的p型金属氧化物半导体（PMOS）晶体管，第一扩散层 区域和与第一扩散区域分离的第二扩散区域，形成在电连接到PMOS晶体管的第一扩散区域的第一阱中的第二n型区域和形成在衬底中的第二p型区域电连接 到PMOS晶体管的第二扩散区域。

公开(公告)号：US07993962B2

公开(公告)日：2011-08-09

申请号：US12614902

申请日：2009-11-09

Applicant: Shih-Hung Chen ,  Hsiang-Lan Lung

Inventor： Shih-Hung Chen ,  Hsiang-Lan Lung

IPC: H01L21/06

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

Abstract: A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the first electrode; a lower phase change member, having a contact surface in electrical contact with the second electrode; and a kernel member disposed between and in electrical contact with the upper and lower phase change members. The phase change cell is formed of material having at least two solid phases, and the lateral extent of the upper and lower phase change members is substantially greater than that of the kernel member. An intermediate insulating layer is disposed between the upper and lower phase change members adjacent to the kernel member.

Abstract translation: 存储器件包括垂直分离并具有相互相对的接触表面的两个电极，它们位于相变单元之间。 相变单元包括上相变构件，具有与第一电极电接触的接触表面; 下部相变构件，具有与第二电极电接触的接触表面; 以及设置在上部和下部相变构件之间并与之电连接的内部构件。 相变单元由具有至少两个固相的材料形成，并且上下相变构件的横向范围基本上大于内核构件的横向范围。 中间绝缘层设置在与内核构件相邻的上下相变构件之间。

公开(公告)号：US20100276654A1

公开(公告)日：2010-11-04

申请号：US12433573

申请日：2009-04-30

Applicant: Shih-Hung Chen ,  Yi-Chou Chen

Inventor： Shih-Hung Chen ,  Yi-Chou Chen

IPC: H01L47/00

CPC classification number: H01L45/122 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1641 ,  H01L45/1675 ,  Y10S977/943

Abstract: Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency.

Abstract translation: 与传统的蘑菇型存储器单元相比，本文所述的存储单元在有源区域的横向边缘处具有增加的电流密度，从而提高了操作电流效率。

公开(公告)号：US20100149703A1

公开(公告)日：2010-06-17

申请号：US12400799

申请日：2009-03-10

Applicant: Chih-Ting Yeh ,  Yung-Chih Liang ,  Shih-Hung Chen

Inventor： Chih-Ting Yeh ,  Yung-Chih Liang ,  Shih-Hung Chen

IPC: H02H9/04

CPC classification number: H03F1/523 ,  H01L27/0266 ,  H03F2200/441

Abstract: An ESD clamp circuit applied to a power amplifier is provided. The ESD clamp circuit includes a first line, a second line, a first circuit, a second circuit, an ESD detecting unit, a buffer unit, and an ESD clamp unit. The first line is coupled to the output terminal of the power amplifier. The first circuit is coupled to the first line. The second circuit is coupled to the first circuit. The ESD detecting unit is coupled to the first circuit and the second line. The buffer unit is coupled to the second circuit, the second line and the ESD detecting unit. The ESD clamp unit is coupled to the buffer unit, the first line and the second line. Therefore, at normal operation mode, the problem of signal loss caused by the leakage current of ESD clamp circuit can be avoided.

Abstract translation: 提供了应用于功率放大器的ESD钳位电路。 ESD钳位电路包括第一线，第二线，第一电路，第二电路，ESD检测单元，缓冲单元和ESD钳位单元。 第一行耦合到功率放大器的输出端。 第一电路耦合到第一线。 第二电路耦合到第一电路。 ESD检测单元耦合到第一电路和第二线。 缓冲单元耦合到第二电路，第二线路和ESD检测单元。 ESD钳位单元耦合到缓冲单元，第一线和第二线。 因此，在正常工作模式下，可以避免由ESD钳位电路的漏电流引起的信号损失问题。

公开(公告)号：US07598023B2

公开(公告)日：2009-10-06

申请号：US11162909

申请日：2005-09-28

Applicant: Yi-Tyng Wu ,  Shih-Hung Chen ,  Huai-Hsuan Tsai ,  Chih-Hung Cheng ,  Chien-Hua Tsai ,  Hsuan-Hsu Chen

Inventor： Yi-Tyng Wu ,  Shih-Hung Chen ,  Huai-Hsuan Tsai ,  Chih-Hung Cheng ,  Chien-Hua Tsai ,  Hsuan-Hsu Chen

IPC: G03F7/00

CPC classification number: G02F1/133502 ,  G02F1/133553 ,  G02F1/136277 ,  Y10S430/151

Abstract: A process for fabricating a micro-display is provided. First, a wafer having a driving circuit thereon is provided. Then, a metallic reflective layer is formed on the wafer. Thereafter, an anti-reflection layer and a patterned photoresist layer are sequentially formed on the metallic reflective layer. Using the patterned photoresist layer as an etching mask, the anti-reflection layer and the metallic reflective layer are etched to form a trench pattern that exposes the surface of the wafer. After that, the patterned photoresist layer is removed. A dielectric layer is formed to cover the anti-reflection layer and fill the trench pattern. Then, a portion of the dielectric layer and the anti-reflection layer are removed to expose the surface of the metallic reflective layer.

Abstract translation: 提供一种制造微型显示器的方法。 首先，提供其上具有驱动电路的晶片。 然后，在晶片上形成金属反射层。 此后，在金属反射层上依次形成抗反射层和图案化的光致抗蚀剂层。 使用图案化的光致抗蚀剂层作为蚀刻掩模，对抗反射层和金属反射层进行蚀刻以形成暴露晶片表面的沟槽图案。 之后，去除图案化的光致抗蚀剂层。 形成介电层以覆盖抗反射层并填充沟槽图案。 然后，去除电介质层和抗反射层的一部分以露出金属反射层的表面。

公开(公告)号：US20070072130A1

公开(公告)日：2007-03-29

申请号：US11162909

申请日：2005-09-28

Applicant: Yi-Tyng Wu ,  Shih-Hung Chen ,  Huai-Hsuan Tsai ,  Chih-Hung Cheng ,  Chien-Hua Tsai ,  Hsuan-Hsu Chen

Inventor： Yi-Tyng Wu ,  Shih-Hung Chen ,  Huai-Hsuan Tsai ,  Chih-Hung Cheng ,  Chien-Hua Tsai ,  Hsuan-Hsu Chen

IPC: G03F7/26

CPC classification number: G02F1/133502 ,  G02F1/133553 ,  G02F1/136277 ,  Y10S430/151

Abstract: A process for fabricating a micro-display is provided. First, a wafer having a driving circuit thereon is provided. Then, a metallic reflective layer is formed on the wafer. Thereafter, an anti-reflection layer and a patterned photoresist layer are sequentially formed on the metallic reflective layer. Using the patterned photoresist layer as an etching mask, the anti-reflection layer and the metallic reflective layer are etched to form a trench pattern that exposes the surface of the wafer. After that, the patterned photoresist layer is removed. A dielectric layer is formed to cover the anti-reflection layer and fill the trench pattern. Then, a portion of the dielectric layer and the anti-reflection layer are removed to expose the surface of the metallic reflective layer.

Abstract translation: 提供一种制造微型显示器的方法。 首先，提供其上具有驱动电路的晶片。 然后，在晶片上形成金属反射层。 此后，在金属反射层上依次形成抗反射层和图案化的光致抗蚀剂层。 使用图案化的光致抗蚀剂层作为蚀刻掩模，对抗反射层和金属反射层进行蚀刻以形成暴露晶片表面的沟槽图案。 之后，去除图案化的光致抗蚀剂层。 形成介电层以覆盖抗反射层并填充沟槽图案。 然后，去除电介质层和抗反射层的一部分以露出金属反射层的表面。

公开(公告)号：US20070018193A1

公开(公告)日：2007-01-25

申请号：US11186086

申请日：2005-07-21

Applicant: Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

Inventor： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

IPC: H01L29/417

CPC classification number: H01L23/62 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract translation: 一种用于静电放电（ESD）保护的半导体器件包括可控硅整流器（SCR），其包括半导体衬底，形成在衬底中的第一阱，在衬底中形成的第二阱，形成在第一阱中的第一p型区 用作阳极，以及部分地形成在第二阱中用作阴极的第一n型区域，形成在包括栅极的第一阱中的p型金属氧化物半导体（PMOS）晶体管，第一扩散层 区域和与第一扩散区域分离的第二扩散区域，形成在电连接到PMOS晶体管的第一扩散区域的第一阱中的第二n型区域和形成在衬底中的第二p型区域电连接 到PMOS晶体管的第二扩散区域。

公开(公告)号：US20060110878A1

公开(公告)日：2006-05-25

申请号：US11285473

申请日：2005-11-21

Applicant: Hsiang Lung ,  Shih-Hung Chen ,  Yi-Chou Chen

Inventor： Hsiang Lung ,  Shih-Hung Chen ,  Yi-Chou Chen

IPC: H01L21/8242 ,  H01L21/20 ,  H01L21/302

CPC classification number: H01L27/112 ,  G11C2213/52 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144 ,  H01L45/1691

Abstract: A method of forming a memory cell comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on the stack. A side wall spacer comprising a programmable resistive material in electrical communication with the first and second electrodes is formed. The side wall spacer is formed by depositing a layer of programmable resistive material over the side wall of the stack, anisotropically etching the layer of programmable resistive material to remove it in areas away from the side wall, and selectively etching the programmable resistive material according to a pattern to define the width of the side wall spacer. In embodiments described herein, the width is about 40 nanometers or less.

公开(公告)号：US08941166B2

公开(公告)日：2015-01-27

申请号：US12981121

申请日：2010-12-29

Applicant: Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L29/788 ,  H01L27/115 ,  H01L21/033 ,  G03F7/00

CPC classification number: H01L27/11565 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/1157 ,  H01L27/11573

Abstract: An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions.

Abstract translation: 集成电路存储器包括一组线，每条线在第一区域中具有平行的X方向线部分，在第二区域具有Y方向线部分。 第二区域偏离第一区域。 X方向线部分的长度比Y方向线部分的长度大得多。 X方向和Y方向线部分具有相应的第一和第二间距，其中第二间距比第一间距大至少3倍。 触点拾取区域在Y方向线部分。 在一些示例中，这些线包括字线或位线。 可以使用多个图案化方法来创建记忆，以产生材料线，然后平行的X方向线部分和平行的Y方向线部分。