公开(公告)号：US20240202123A1

公开(公告)日：2024-06-20

申请号：US18594091

申请日：2024-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0815 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F15/80

CPC classification number: G06F12/0815 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3853 ,  G06F9/3887 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30065 ,  G06F9/325 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/6026 ,  G06F2212/621

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.

公开(公告)号：US20240126549A1

公开(公告)日：2024-04-18

申请号：US18544619

申请日：2023-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F9/30043 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3861 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to operational units for use as operands. A promotion unit optionally increases date element data size by an integral power of 2 either zero filing or sign filling the additional bits. A decimation unit optionally decimates data elements by an integral factor of 2. For ease of implementation the promotion factor must be greater than or equal to the decimation factor.

公开(公告)号：US11934833B2

公开(公告)日：2024-03-19

申请号：US17557712

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0875

CPC classification number: G06F9/30149 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/3016 ,  G06F9/345 ,  G06F9/3824 ,  G06F9/383 ,  G06F12/0875 ,  G06F2212/452

Abstract: A streaming engine employed in a digital signal processor specifies a fixed read only data stream. Once fetched the data stream is stored in two head registers for presentation to functional units in the fixed order. Data use by the functional unit is preferably controlled using the input operand fields of the corresponding instruction. A first read only operand coding supplies data from the first head register. A first read/advance operand coding supplies data from the first head register and also advances the stream to the next sequential data elements. Corresponding second read only operand coding and second read/advance operand coding operate similarly with the second head register. A third read only operand coding supplies double width data from both head registers.

公开(公告)号：US20240054098A1

公开(公告)日：2024-02-15

申请号：US18496013

申请日：2023-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0862 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38 ,  G06F12/02

CPC classification number: G06F12/0862 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/383 ,  G06F12/0207 ,  G06F2212/6026

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.

公开(公告)号：US20240020121A1

公开(公告)日：2024-01-18

申请号：US18476604

申请日：2023-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Brett L. Huber ,  Duc Bui

IPC: G06F9/30 ,  G06F18/24

CPC classification number: G06F9/30036 ,  G06F9/3013 ,  G06F18/24

Abstract: A processor includes a functional unit, and a set of vector registers coupled to the functional unit. The processor executes an instruction to cause the functional unit to classify each value of multiple floating-point values stored in a first vector register of the set of vector registers, and store in a second vector register of the set of registers multiple elements that each indicate a respective classification of a respective value of the multiple floating-point values. The first and second vector registers may be source and destination vector registers, and each may be specified by the instruction. The classify and store operations may also be specified by the instruction. The instruction may be embodied on a device-readable medium.

公开(公告)号：US20230367717A1

公开(公告)日：2023-11-16

申请号：US18357748

申请日：2023-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson

IPC: G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F12/0897 ,  G06F9/38 ,  G06F13/16

CPC classification number: G06F12/0875 ,  G06F9/30047 ,  G06F12/0862 ,  G06F12/0897 ,  G06F9/383 ,  G06F13/1668 ,  G06F12/0811

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.

公开(公告)号：US20230359565A1

公开(公告)日：2023-11-09

申请号：US18357732

申请日：2023-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0897 ,  G06F9/30 ,  G06F12/0815 ,  G06F12/0875 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/04

CPC classification number: G06F12/0897 ,  G06F9/3013 ,  G06F12/0815 ,  G06F12/0875 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3853 ,  G06F9/3887 ,  G06F12/0862 ,  G06F9/3877 ,  G06F12/04 ,  G06F9/30101 ,  G06F2212/452 ,  G06F2212/6026 ,  G06F2212/1056 ,  G06F2212/454 ,  G06F9/3552

Abstract: A streaming engine employed in a digital data processor may specify a fixed read-only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.

公开(公告)号：US11803505B2

公开(公告)日：2023-10-31

申请号：US17735255

申请日：2022-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/42 ,  G06F13/362

CPC classification number: G06F13/4252 ,  G06F13/362

Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

公开(公告)号：US11803477B2

公开(公告)日：2023-10-31

申请号：US17947371

申请日：2022-09-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/35 ,  G06F12/0862 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38 ,  G06F12/02

CPC classification number: G06F12/0862 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/383 ,  G06F12/0207 ,  G06F2212/6026

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.

公开(公告)号：US11709778B2

公开(公告)日：2023-07-25

申请号：US16916254

申请日：2020-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson

IPC: G06F9/38 ,  G06F12/0802 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F12/0897 ,  G06F13/16 ,  G06F12/0811 ,  G06F12/10

CPC classification number: G06F12/0875 ,  G06F9/30047 ,  G06F9/383 ,  G06F12/0862 ,  G06F12/0897 ,  G06F13/1668 ,  G06F12/0811 ,  G06F12/10 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/6026

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.