-
公开(公告)号：US09711646B2
公开(公告)日：2017-07-18
申请号：US14230223
申请日：2014-03-31
Applicant: United Microelectronics Corp.
Inventor： Yu-Ping Wang , Jyh-Shyang Jenq , Yu-Hsiang Lin , Hsuan-Hsu Chen , Chien-Hao Chen , Yi-Han Ye
CPC classification number: H01L29/785 , H01L29/66795
Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.
-
公开(公告)号：US20160104786A1
公开(公告)日：2016-04-14
申请号：US14543914
申请日：2014-11-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Yang , Yu-Feng Liu , Jian-Cun Ke , Chia-Fu Hsu , En-Chiuan Liou , Ssu-I Fu , Chi-Mao Hsu , Nien-Ting Ho , Yu-Ru Yang , Yu-Ping Wang , Chien-Ming Lai , Yi-Wen Chen , Yu-Ting Tseng , Ya-Huei Tsai , Chien-Chung Huang , Tsung-Yin Hsieh , Hung-Yi Wu
IPC: H01L29/49 , H01L27/092 , H01L21/28 , H01L21/321 , H01L27/088 , H01L21/8234
CPC classification number: H01L29/4966 , H01L21/28088 , H01L21/321 , H01L21/823431 , H01L21/82345 , H01L27/088 , H01L29/517 , H01L29/66545
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.
Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。
-
公开(公告)号：US12290005B2
公开(公告)日：2025-04-29
申请号：US18679437
申请日：2024-05-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
-
公开(公告)号：US20250107454A1
公开(公告)日：2025-03-27
申请号：US18976359
申请日：2024-12-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , Chen-Yi Weng , Chin-Yang Hsieh , I-Ming Tseng , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.
-
公开(公告)号：US12262647B2
公开(公告)日：2025-03-25
申请号：US18592553
申请日：2024-03-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
-
Patent Agency Ranking
公开(公告)号：US12262544B2
公开(公告)日：2025-03-25
申请号：US18595363
申请日：2024-03-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer, and patterning the second SOT layer and the passivation layer.
-
公开(公告)号：US20250048936A1
公开(公告)日：2025-02-06
申请号：US18919382
申请日：2024-10-17
Applicant: United Microelectronics Corp.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Chen-Yi Weng , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
-
公开(公告)号：US20250040149A1
公开(公告)日：2025-01-30
申请号：US18916730
申请日：2024-10-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Huei Tsai , Rai-Min Huang , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.
-
公开(公告)号：US12150315B2
公开(公告)日：2024-11-19
申请号：US18395649
申请日：2023-12-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Huei Tsai , Rai-Min Huang , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.
-
公开(公告)号：US20240371695A1
公开(公告)日：2024-11-07
申请号：US18204398
申请日：2023-06-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chuan-Lan Lin , Yu-Ping Wang , Chien-Ting Lin , Chu-Fu Lin , Chun-Ting Yeh , Chung-Hsing Kuo
Abstract: A method for fabricating a semiconductor device includes the steps of first providing a wafer, forming a scribe line on a front side of the wafer, performing a plasma dicing process to dice the wafer along the scribe line without separating the wafer completely, performing a laminating process to form a tape on the front side of the wafer, performing a grinding process on a backside of the wafer, and then performing an expanding process to divide the wafer into chips.
-
-
-
-
-
-
-
-
-
Search Results
187
records
(took 0.015 seconds)
