公开(公告)号：US07923322B2

公开(公告)日：2011-04-12

申请号：US11234328

申请日：2005-09-23

申请人： Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

发明人： Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

IPC分类号： H01L21/8242

CPC分类号： H01L21/28525 ,  C23C16/04 ,  C23C16/24 ,  H01L21/28562 ,  H01L21/31604 ,  H01L21/32051 ,  H01L21/76879 ,  H01L28/60 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/7834

摘要： A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed over the first capacitor electrode. The substrate with the substantially crystalline capacitor dielectric layer is provided within a chemical vapor deposition reactor. Such substrate has an exposed substantially amorphous material. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the substantially crystalline capacitor dielectric layer relative to the exposed substantially amorphous material, and the polysilicon is formed into a second capacitor electrode.

摘要翻译： 形成电容器的方法包括在衬底上形成第一电容器电极。 在第一电容器电极上形成基本上结晶的电容器电介质层。 具有基本上结晶的电容器电介质层的衬底设置在化学气相沉积反应器内。 这种衬底具有暴露的基本无定形的材料。 包含硅的气态前体在有效基本上选择性地在基本上结晶的电容器电介质层上沉积多晶硅相对于暴露的基本无定形材料的条件下被馈送到化学气相沉积反应器，并且多晶硅形成第二电容器电极。

公开(公告)号：US07906393B2

公开(公告)日：2011-03-15

申请号：US10767298

申请日：2004-01-28

申请人： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Kevin L. Beaman ,  Ronald A. Weimer ,  Cem Basceri ,  David J. Kubista

发明人： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Kevin L. Beaman ,  Ronald A. Weimer ,  Cem Basceri ,  David J. Kubista

IPC分类号： H01L21/8242

CPC分类号： H01L28/40 ,  H01L21/3141 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/84

摘要： The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.

摘要翻译： 本公开提供小尺寸电容器（例如，DRAM电容器）以及形成这种电容器的方法。 一个示例性实施例提供了一种制造电容器的方法，该电容器包括顺序地形成第一电极，电介质层和第二电极。 可以通过以下方式形成至少一个电极：a）使两个前体反应以第一沉积速率沉积第一导电层，以及b）通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层 至少一层单层，并将该前体层暴露于另一种前体以形成纳米层反应产物。 第二导电层可以与介电层接触并具有不大于约的厚度。

公开(公告)号：US20100176366A1

公开(公告)日：2010-07-15

申请号：US12320008

申请日：2009-01-14

申请人： Chu-Chen Fu ,  Tanmay Kumar ,  Er-Xuan Ping ,  Huiwan Xu

发明人： Chu-Chen Fu ,  Tanmay Kumar ,  Er-Xuan Ping ,  Huiwan Xu

IPC分类号： H01L45/00 ,  H01L21/308

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1616 ,  H01L45/1675

摘要： A nonvolatile memory cell includes a storage element, the storage element comprising a carbon material, a steering element located in series with the storage element, and a metal silicide layer located adjacent to the carbon material. A method of making a device includes forming a metal silicide over a silicon layer, forming a carbon layer over the metal silicide layer, forming a barrier layer over the carbon layer, and patterning the carbon layer, the metal silicide layer, and the silicon layer to form an array of pillars.

摘要翻译： 非易失性存储单元包括存储元件，所述存储元件包括碳材料，与所述存储元件串联定位的操舵元件和位于所述碳材料附近的金属硅化物层。 制造器件的方法包括在硅层上形成金属硅化物，在金属硅化物层上形成碳层，在碳层上形成阻挡层，并对碳层，金属硅化物层和硅层进行构图 形成一系列的柱子。

公开(公告)号：US20090311843A1

公开(公告)日：2009-12-17

申请号：US12547197

申请日：2009-08-25

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

IPC分类号： H01L21/02

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

摘要翻译： 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

公开(公告)号：US07579232B1

公开(公告)日：2009-08-25

申请号：US12216924

申请日：2008-07-11

申请人： Er-Xuan Ping ,  Randhir Thakur ,  Klaus Scheugraf

发明人： Er-Xuan Ping ,  Randhir Thakur ,  Klaus Scheugraf

IPC分类号： H01L21/8234 ,  H01L21/8222 ,  H01L21/425

CPC分类号： H01L27/1021 ,  H01L21/7688 ,  H01L27/101

摘要： A method of making a semiconductor device includes forming a pillar shaped semiconductor device surrounded by an insulating layer such that a contact hole in the insulating layer exposes an upper surface of the semiconductor device. The method also includes forming a shadow mask layer over the insulating layer such that a portion of the shadow mask layer overhangs a portion of the contact hole, forming a conductive layer such that a first portion of the conductive layer is located on the upper surface of the semiconductor device exposed in the contact hole and a second portion of the conductive layer is located over the shadow mask layer, and removing the shadow mask layer and the second portion of the conductive layer.

摘要翻译： 制造半导体器件的方法包括形成由绝缘层包围的柱状半导体器件，使得绝缘层中的接触孔露出半导体器件的上表面。 该方法还包括在绝缘层上形成荫罩层，使得阴影掩模层的一部分悬垂在接触孔的一部分上，形成导电层，使得导电层的第一部分位于 暴露在接触孔中的半导体器件和导电层的第二部分位于荫罩层之上，并且去除荫罩层和导电层的第二部分。

公开(公告)号：US07258892B2

公开(公告)日：2007-08-21

申请号：US10733523

申请日：2003-12-10

申请人： Kevin L. Beaman ,  Trung T. Doan ,  Lyle D. Breiner ,  Ronald A. Weimer ,  Er-Xuan Ping ,  David J. Kubista ,  Cem Basceri ,  Lingyi A. Zheng

发明人： Kevin L. Beaman ,  Trung T. Doan ,  Lyle D. Breiner ,  Ronald A. Weimer ,  Er-Xuan Ping ,  David J. Kubista ,  Cem Basceri ,  Lingyi A. Zheng

IPC分类号： C23C16/52 ,  B05C11/00 ,  H05B1/02

CPC分类号： C23C16/00 ,  C23C16/46

摘要： The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.

摘要翻译： 本公开提供了用于控制温度的方法和系统。 该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。 一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。 通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。 目标温度可以根据斜坡曲线来确定，但是一个实施例中的控制温度在第一温度和第二温度之间交替。

公开(公告)号：US20060244092A1

公开(公告)日：2006-11-02

申请号：US11477958

申请日：2006-06-28

申请人： Lingyi Zheng ,  Er-Xuan Ping

发明人： Lingyi Zheng ,  Er-Xuan Ping

IPC分类号： H01L29/00

CPC分类号： H01L21/02175 ,  C23C16/34 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/3141 ,  H01L21/76841 ,  H01L28/60

摘要： The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions being nearer the dielectric material than the other. The portion of the metal nitride nearest the dielectric material is formed from a non-halogenated metal-containing precursor, and the portion of the metal nitride further from the dielectric material is formed from a halogenated metal-containing precursor. The methodology of the present invention can be utilized for forming capacitor constructions, with the portion of the metal nitride formed from the halogenated metal-containing precursor being incorporated into a capacitor electrode.

公开(公告)号：US20060243196A1

公开(公告)日：2006-11-02

申请号：US11478401

申请日：2006-06-29

申请人： Jingyan Zhang ,  Er-Xuan Ping

发明人： Jingyan Zhang ,  Er-Xuan Ping

IPC分类号： C30B25/00 ,  C30B23/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： C30B29/06 ,  C30B23/02 ,  C30B25/18

摘要： Methods of cleaning substrates and growing epitaxial silicon thereon are provided. Wafers are exposed to a plasma for a sufficient time prior to epitaxial silicon growth, in order to clean the wafers. The methods exhibit enhanced selectivity and reduced lateral growth of epitaxial silicon. The wafers may have dielectric areas that are passivated by the exposure of the wafer to a plasma.

公开(公告)号：US07119369B2

公开(公告)日：2006-10-10

申请号：US10758059

申请日：2004-01-15

申请人： Zhongze Wang ,  Chih-Chen Cho ,  Er-Xuan Ping

发明人： Zhongze Wang ,  Chih-Chen Cho ,  Er-Xuan Ping

IPC分类号： H01L27/108

CPC分类号： H01L29/66651 ,  H01L21/76264 ,  H01L29/0653

摘要： A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline material formed on the bulk semiconductor substrate so as to extend away from each side of the channel region.

摘要翻译： 场效应晶体管具有体半导体衬底中的沟道区，沟道区的第一侧上的第一源极/漏极区，沟道区的第二侧上的第二源极/漏极区和外延的延伸 形成在体半导体衬底上以便从沟道区的每一侧延伸的单晶材料。

公开(公告)号：US20060196538A1

公开(公告)日：2006-09-07

申请号：US11416871

申请日：2006-05-02

申请人： David Kubista ,  Trung Doan ,  Lyle Breiner ,  Ronald Weimer ,  Kevin Beaman ,  Er-Xuan Ping ,  Lingyi Zheng ,  Cem Basceri

发明人： David Kubista ,  Trung Doan ,  Lyle Breiner ,  Ronald Weimer ,  Kevin Beaman ,  Er-Xuan Ping ,  Lingyi Zheng ,  Cem Basceri

IPC分类号： F17D1/16 ,  C23C16/00

CPC分类号： C23C16/45544 ,  C23C16/4412 ,  Y10T137/0396

摘要： Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers are disclosed herein. In one embodiment, the system includes a gas phase reaction chamber, a first exhaust line coupled to the reaction chamber, first and second traps each in fluid communication with the first exhaust line, and a vacuum pump coupled to the first exhaust line to remove gases from the reaction chamber. The first and second traps are operable independently to individually and/or jointly collect byproducts from the reaction chamber. It is emphasized that this Abstract is provided to comply with the rules requiring an abstract. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 用于在反应室中将材料沉积到工件上的系统以及用于从反应室除去副产物的方法在此公开。 在一个实施例中，系统包括气相反应室，连接到反应室的第一排气管线，与第一排气管线流体连通的第一和第二阱，以及耦合到第一排气管线以除去气体的真空泵 从反应室。 第一和第二捕集器独立地可操作地单独地和/或共同地从反应室收集副产物。 要强调的是提供本摘要以符合要求摘要的规则。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。