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    Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry
    102.
    发明授权
    Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry 有权

    公开(公告)号：US07057257B2

    公开(公告)日：2006-06-06

    申请号：US10071453

    申请日：2002-02-08

    申请人： Luan C. Tran

    发明人： Luan C. Tran

    IPC分类号： H01L27/108

    CPC分类号： H01L21/823481 ,  H01L27/10894 ,  H01L27/10897

    摘要： Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. In another embodiment, a plurality of shallow trench isolation regions are formed within a substrate and define a plurality of active areas having widths at least some of which being no greater than about one micron (or less), with some of the widths preferably being different. One or more gate lines may be coupled to the respective active areas to provide individual transistors, with the transistors corresponding to the active areas having the different widths having different threshold voltages. In another embodiment, two field effect transistors are fabricated having different threshold voltages without using a separate channel implant for one of the transistors versus the other.

    Isolation device over field in a memory device
    103.
    发明授权
    Isolation device over field in a memory device 失效
    隔离设备在存储设备中的字段

    公开(公告)号：US07020039B2

    公开(公告)日：2006-03-28

    申请号：US10998483

    申请日：2004-11-29

    申请人： Luan C. Tran ,  Stephen R. Porter ,  Scot M. Graham ,  Steven E. Howell

    发明人： Luan C. Tran ,  Stephen R. Porter ,  Scot M. Graham ,  Steven E. Howell

    IPC分类号： G11C7/00

    CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  G11C29/816 ,  G11C2207/002 ,  G11C2207/005 ,  Y10S257/906

    摘要： A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.

    摘要翻译： 存储器件包括位于存储器单元之间的隔离器件。 多个隔离线在正常操作期间将隔离装置连接到正电压，但是仍然使隔离装置保持在关闭状态以提供存储单元之间的隔离。 在隔离线路和电源节点之间放置电流控制电路，用于在任何一个隔离装置发生偏转的情况下减少在隔离线路与功率节点之间流动的电流。

    Method to prevent bit line capacitive coupling
    106.
    发明授权
    Method to prevent bit line capacitive coupling 有权
    防止位线电容耦合的方法

    公开(公告)号：US06894915B2

    公开(公告)日：2005-05-17

    申请号：US10295225

    申请日：2002-11-15

    申请人： Luan C. Tran

    发明人： Luan C. Tran

    IPC分类号： G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242

    CPC分类号： H01L27/10885 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/10888 ,  H01L27/10891

    摘要： Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A memory cell is formed in a triple well structure that includes a substrate, the buried layer, and an epitaxial layer. The substrate, buried layer, and epitaxial layer include voltage contacts that allow for the wells to be biased to a de voltage level. The memory cell includes a transistor which is formed on the epitaxial layer, the transistor including a source and drain region separated by a channel region. The trench bit line is formed within the buried layer, and is coupled to the drain region of the transistor by a bit contact.

    摘要翻译： 提供了利用在掩埋层内形成的沟槽位线的存储单元的结构，系统和方法。 存储单元形成在三阱结构中，其包括衬底，掩埋层和外延层。 衬底，掩埋层和外延层包括允许阱被偏置到电压电平的电压触点。 存储单元包括形成在外延层上的晶体管，晶体管包括由沟道区分开的源极和漏极区域。 沟槽位线形成在掩埋层内，并通过位接触耦合到晶体管的漏极区域。

    Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random
    107.
    发明授权
    Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random 失效
    形成接触开口的半导体加工方法，形成存储器电路的方法，形成电连接的方法以及形成动态随机存取存储器（电容）电路的方法

    公开(公告)号：US06764934B2

    公开(公告)日：2004-07-20

    申请号：US10137100

    申请日：2002-05-01

    申请人： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

    发明人： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

    IPC分类号： H04L2144

    CPC分类号： H01L27/10888 ,  H01L21/32051 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

    摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

    摘要翻译： 描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。 在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。 位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。 材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。 随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

    Low voltage high performance semiconductor devices and methods
    109.
    发明授权
    Low voltage high performance semiconductor devices and methods 有权
    低电压高性能半导体器件及方法

    公开(公告)号：US06492693B2

    公开(公告)日：2002-12-10

    申请号：US09903623

    申请日：2001-07-13

    申请人： Luan C. Tran

    发明人： Luan C. Tran

    IPC分类号： H01L2978

    CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1083

    摘要： A method for adjusting Vt while minimizing parasitic capacitance fiord low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.

    摘要翻译： 一种在最小化寄生电容低压高速半导体器件的同时调整Vt的方法。 该方法使用阴影效应和倾斜冲击穿过垂直结构之间的预防植入物来提供分级植入物。 植入角度大于或等于S / H的反正切，其中S是水平距离，H是这种垂直结构的高度。

    REFERENCE CHARGE GENERATOR, A METHOD FOR PROVIDING A REFERENCE CHARGE FROM A REFERENCE CHARGE GENERATOR, A METHOD OF OPERATING A REFERENCE CHARGE GENERATOR AND A DRAM MEMORY CIRCUIT FORMED USING MEMORY CELLS HAVING AN AREA OF 6F2
    110.
    发明授权
    REFERENCE CHARGE GENERATOR, A METHOD FOR PROVIDING A REFERENCE CHARGE FROM A REFERENCE CHARGE GENERATOR, A METHOD OF OPERATING A REFERENCE CHARGE GENERATOR AND A DRAM MEMORY CIRCUIT FORMED USING MEMORY CELLS HAVING AN AREA OF 6F2 有权
    参考充电发生器，用于从参考充电发生器提供参考充电的方法，操作参考充电发生器的方法和使用具有6F2的区域的存储器电池形成的DRAM存储器电路

    公开(公告)号：US06411555B1

    公开(公告)日：2002-06-25

    申请号：US09812729

    申请日：2001-03-19

    申请人： Luan C. Tran

    发明人： Luan C. Tran

    IPC分类号： G11C700

    CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C11/4074 ,  H01L27/10897

    摘要： The present invention provides a method for providing a reference charge from a reference charge generator. The method includes coupling a pair of non-planar reference capacitors each having a capacitance CREF between a power supply voltage V and ground to provide a first stored charge QREF, where QREF=CREFV/2, decoupling the pair of reference capacitors from the power supply voltage V and coupling the first stored charge QREF from the pair of reference capacitors to a bitline.

    摘要翻译： 本发明提供了一种用于从参考电荷发生器提供参考电荷的方法。 该方法包括在电源电压V和地之间耦合一对具有电容CREF的非平面参考电容器，以提供第一存储电荷QREF，其中QREF = CREFV / 2，将一对参考电容器与电源 电压V并将来自该对参考电容器的第一存储电荷QREF耦合到位线。