公开(公告)号：US5941938A

公开(公告)日：1999-08-24

申请号：US759043

申请日：1996-12-02

Applicant: John S. Thayer

Inventor： John S. Thayer

IPC: G06F7/50 ,  G06F7/509 ,  G06F7/38

CPC classification number: G06F7/5095

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract translation: 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

公开(公告)号：US5924122A

公开(公告)日：1999-07-13

申请号：US818757

申请日：1997-03-14

Applicant: Wayne M. Cardoza ,  Kathleen D. Morse ,  Richard B. Gillett, Jr. ,  Charles Kaufman

Inventor： Wayne M. Cardoza ,  Kathleen D. Morse ,  Richard B. Gillett, Jr. ,  Charles Kaufman

IPC: H04L29/06 ,  H04L29/08 ,  G06F12/16

CPC classification number: H04L29/06 ,  H04L69/324

Abstract: An error recovery method and apparatus has specific application in a networking arrangement having a plurality of individual processing nodes which communicate via shared memory space. For error recovery, the system uses a reliable error count, the value of which is maintained by all of the nodes. When an error is detected, the error count is incremented, and all of the active nodes are provided with the new error count. Any of the nodes can run the error recovery method, and may gain exclusive access to the network by acquiring an error recovery spinlock. Once the spinlock is acquired, the node holding the spinlock increments the error count and confirms that all active nodes have received the new error count. The spinlock is thereafter released.

Abstract translation: 一种错误恢复方法和装置在具有通过共享存储器空间通信的多个单独处理节点的网络布置中具有特定应用。 对于错误恢复，系统使用可靠的错误计数，其值由所有节点维护。 当检测到错误时，错误计数增加，并且所有活动节点都被提供新的错误计数。 任何节点都可以运行错误恢复方法，并可以通过获取错误恢复自旋锁来获得对网络的独占访问权限。 一旦获得了自旋锁，则保持自旋锁的节点会增加错误计数，并确认所有活动节点已收到新的错误计数。 螺旋锁随后释放。

公开(公告)号：US5913058A

公开(公告)日：1999-06-15

申请号：US941623

申请日：1997-09-30

Applicant: Thomas J. Bonola

Inventor： Thomas J. Bonola

IPC: G06F9/445 ,  G06F9/06 ,  G06F13/00

CPC classification number: G06F9/4411

Abstract: A system and method for using real mode BIOS calls to load an executable program for execution on a dedicated I/O processor before device drivers which communicate with the I/O processor have been loaded by an operating system. In the preferred embodiment, the system comprises a plurality of x86 processors coupled to a system memory. One of the x86 processors is designated as a dedicated I/O processor. A storage device stores an operating system for execution on the remaining processors, an executable program for executing on the dedicated I/O processor, such as a real-time kernel, and a device driver which is operable to execute on the remaining processors and to communicate with the real-time kernel executing on the I/O processor to perform I/o operations on an I/O device. The storage device also stores a loader program which is loaded by the operating system executing on a first of the remaining processors early in the process of booting the operating system. The loader program executing on the first processor creates a real mode interface in order to switch the first processor to real mode so that a real mode code portion of the loader can execute BIOS INT13 disk requests to read the real-time kernel from the storage device. Creating the real mode interface comprises saving the protected mode state of the first processor and of the system's interrupt control logic. After saving the states of the first processor and interrupt control logic, the loader program programs the interrupt control logic to simulate a real mode environment. The loader program also provides a "tiled mapping" of memory addresses such that the transition may be made from real mode to protected mode and vice versa to facilitate the x86 processor real mode and protected mode physical address computation differences.

Abstract translation: 在与I / O处理器通信的设备驱动程序已由操作系统加载的情况下，使用实模式BIOS调用来加载可执行程序以在专用I / O处理器上执行的系统和方法。 在优选实施例中，系统包括耦合到系统存储器的多个x86处理器。 其中一个x86处理器被指定为专用的I / O处理器。 存储装置存储用于在其余处理器上执行的操作系统，用于在诸如实时内核的专用I / O处理器上执行的可执行程序以及可操作以在其余处理器上执行的设备驱动器 与在I / O处理器上执行的实时内核进行通信，以在I / O设备上执行I / O操作。 存储装置还存储在启动操作系统的过程中提前在操作系统中加载的加载程序，该操作系统在第一个剩余的处理器上执行。 在第一处理器上执行的加载器程序创建实模式接口，以便将第一处理器切换到实模式，使得加载器的实模式代码部分可以执行BIOS INT13盘请求以从存储设备读取实时内核 。 创建实模式接口包括保存第一处理器和系统的中断控制逻辑的保护模式状态。 在保存第一处理器和中断控制逻辑的状态之后，加载器程序对中断控制逻辑进行编程以模拟实模式环境。 加载程序还提供了存储器地址的“平铺映射”，使得可以从实模式转换到保护模式，反之亦然，以便于x86处理器实模式和保护模式物理地址计算差异。

公开(公告)号：US5913034A

公开(公告)日：1999-06-15

申请号：US709208

申请日：1996-08-27

Applicant: Tom R. Malcolm

Inventor： Tom R. Malcolm

IPC: G06F1/16 ,  H04L12/24 ,  H05K7/16 ,  G06F17/00

CPC classification number: H04L12/24 ,  G06F1/16 ,  H04L41/00

Abstract: An administrator station for administering and maintaining a plurality of computer network and/or communications servers. A low profile clam-shell display and keyboard apparatus, as utilized in a portable notebook computer, is used to replace a rack mounted cathode ray tube video monitor, keyboard and cursor control devices, and an electromechanical switcher. An interface apparatus translates the video output, keyboard and mouse signals of a plurality of computer servers to a format that may be communicated to the administrator station either through a physical connection or by means of wireless communications such as infrared, cellular or spread spectrum radio. When not in use, the administrator station may be stored in a low profile rack panel located in a rack cabinet having a plurality of computer servers mounted therein. Alternatively, the administrator station may be moved from one rack cabinet of computer servers to another. The administrator station may also be comprised of a standard computer, either portable or desk top, and use a wireless or wired communication means adapted to communicate with a plurality of computer servers in different locations.

Abstract translation: 管理站，用于管理和维护多个计算机网络和/或通信服务器。 用在便携式笔记本计算机中的低调蛤壳式显示器和键盘装置用于替代机架安装的阴极射线管视频监视器，键盘和光标控制装置以及机电切换器。 接口装置将多个计算机服务器的视频输出，键盘和鼠标信号转换成可以通过物理连接或通过诸如红外，蜂窝或扩频无线电之类的无线通信传送到管理员站的格式。 当不使用时，管理员站可以存储在位于其中安装有多个计算机服务器的机架式机柜中的低调机架面板中。 或者，管理员站可以从计算机服务器的一个机架柜移动到另一个。 管理员站也可以由便携式或桌面式的标准计算机组成，并且使用适于与不同位置的多个计算机服务器进行通信的无线或有线通信装置。

公开(公告)号：US5893145A

公开(公告)日：1999-04-06

申请号：US757115

申请日：1996-12-02

Applicant: John S. Thayer ,  Gary W. Thome ,  Brian E. Longhenry

Inventor： John S. Thayer ,  Gary W. Thome ,  Brian E. Longhenry

IPC: G06F7/57 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/38 ,  G06F12/00

CPC classification number: G06F7/57 ,  G06F17/147 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3824 ,  G06F2207/3828

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract translation: 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

公开(公告)号：US5889970A

公开(公告)日：1999-03-30

申请号：US853289

申请日：1997-05-09

Applicant: Ronald Timothy Horan ,  Sompong Paul Olarig

Inventor： Ronald Timothy Horan ,  Sompong Paul Olarig

IPC: G06F3/14 ,  G06F12/08 ,  G09G5/393 ,  G06F13/40

CPC classification number: G06F3/14 ,  G06F12/0875 ,  G09G5/393 ,  G09G2360/121

Abstract: A core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. A common bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and either an AGP or PCI device(s). The core logic chip set also has an AGP/PCI arbiter having additional Request ("REQ") and Grant ("GNT") signal lines so that more than one PCI device may be utilized on the additional PCI bus. Selection of the type of bus bridge (AGP or PCI) in the core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or PCI device connected to the common bus.

Abstract translation: 在计算机系统中提供了一种核心逻辑芯片组，其可被配置为加速图形端口（“AGP”）总线与主机和存储器总线之间的桥接器，作为附加外围部件互连（“PCI”） 总线和主机和内存总线，或作为主PCI总线和附加PCI总线之间的桥梁。 具有PCI和AGP接口信号的公共总线连接到核心逻辑芯片组和AGP或PCI设备。 核心逻辑芯片组还具有具有附加请求（“REQ”）和Grant（“GNT”）信号线的AGP / PCI仲裁器，使得可以在附加PCI总线上使用多于​​一个PCI设备。 在核心逻辑芯片组中选择总线桥（AGP或PCI）的类型可以通过硬件信号输入，计算机系统配置或上电自检（“POST”）期间的软件进行。 也可以在检测到连接到公共总线的AGP或PCI设备时确定软件配置。

公开(公告)号：US5821641A

公开(公告)日：1998-10-13

申请号：US690640

申请日：1996-07-30

Applicant: Frank J. Demo ,  Edward R. Stanford

Inventor： Frank J. Demo ,  Edward R. Stanford

IPC: G06F1/26 ,  H01H35/00

CPC classification number: G06F1/26 ,  Y10T307/826 ,  Y10T307/832 ,  Y10T307/937 ,  Y10T307/944

Abstract: A device for enabling and disabling the supply of power from a power source to a computer, the power source having a primary side and a secondary side, the device including an interlock switch connected to the computer, the interlock switch selectably positionable between open and closed positions; and two optocouplers coupled in parallel, both of which are referenced to the secondary side of the power source. When the interlock switch is closed, the first optocoupler is active. This enables the supply of power from the power source to the computer. When the interlock switch opens, the first optocoupler shuts off. This disables the supply of power from the power source to the computer. Further when the interlock switch is opened, the second optocoupler is saturated. This overrides the regulation feedback circuitry from regulating the power supplied by the power source driving the power outputted to the computer to zero. When the interlock switch is closed, the second optocoupler operates in the linear region. This enables the regulation feedback circuitry to regulate the power supplied by the power source to the computer.

Abstract translation: 一种用于启用和禁用从电源向计算机供电的装置，所述电源具有初级侧和次级侧，所述装置包括连接到所述计算机的互锁开关，所述联锁开关可选择地定位在打开和关闭之间 职位; 并联并联的两个光耦合器，它们均以电源的次级侧为参考。 当互锁开关闭合时，第一个光耦合器处于活动状态。 这使得能够从电源向计算机供电。 当互锁开关打开时，第一个光耦合器关闭。 这将禁止从电源向计算机供电。 此外，当互锁开关打开时，第二个光耦合器饱和。 这将覆盖调节反馈电路，以调节由驱动输出到计算机的电力为零的电源提供的功率。 当互锁开关闭合时，第二个光耦合器在线性区域中运行。 这使得调节反馈电路能够调节由电源向计算机提供的功率。

公开(公告)号：US5819156A

公开(公告)日：1998-10-06

申请号：US783608

申请日：1997-01-14

Applicant: Brian V. Belmont

Inventor： Brian V. Belmont

IPC: H04N5/44 ,  H04N21/41 ,  H04N21/81 ,  H04N7/16

CPC classification number: H04N5/4401 ,  H04N21/44222 ,  H04N21/443 ,  H04N21/4782 ,  G09G2340/125 ,  H04N21/4316

Abstract: A TV/PC convergence device, operable in a television mode, a computer mode and a combination television/computer mode, includes a display, a computer and a tracking device. The display receives and displays images in all three modes. The computer executes programs and is operable in the computer mode and the combination television/computer mode. The tracking device, which is coupled to the display and computer, tracks, records, and reports select uses of the display and the computer during each of the television mode, the computer mode and the combination television/computer mode.

Abstract translation: 可在电视模式，计算机模式和组合电视/计算机模式下操作的TV / PC会聚装置包括显示器，计算机和跟踪装置。 显示器以所有三种模式接收和显示图像。 计算机执行程序并且可以在计算机模式和组合电视/计算机模式下操作。 耦合到显示器和计算机的跟踪装置在电视模式，计算机模式和组合电视/计算机模式期间跟踪，记录和报告显示器和计算机的选择使用。

公开(公告)号：US5809549A

公开(公告)日：1998-09-15

申请号：US801738

申请日：1997-02-14

Applicant: Gary W. Thome ,  Michael J. Collins

Inventor： Gary W. Thome ,  Michael J. Collins

IPC: G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G06F13/28

CPC classification number: G11C8/18 ,  G06F13/4243 ,  G11C7/1018 ,  G11C7/22

Abstract: Burst SRAMs designed for operation at a given data rate corresponding to the frequency of a first clock signal but capable of operation using a higher frequency clock signal. The burst SRAMs are preferably incorporated into the cache memory of a second level cache coupled to the processor bus in a computer system, where the computer system is preferably based on a 66-MHz P5 microprocessor. A cache controller, preferably incorporated within a memory controller, controls operation of the second level cache memory by providing the address load and address advance signals. The burst SRAMs are capable of recognizing the faster clock pulses, as well as the shorter pulses asserted on the address load and address advance signals. The address control signals are asserted and then negated during consecutive clock cycles of the faster clock signal, so that the burst SRAMs effectively operate at the same data rate corresponding to the lower frequency clock signal.

Abstract translation: 突发SRAM被设计为以对应于第一时钟信号的频率但能够使用较高频率时钟信号操作的给定数据速率进行操作。 突发SRAM优选地并入计算机系统中耦合到处理器总线的第二级高速缓冲存储器中，其中计算机系统优选地基于66MHz P5微处理器。 优选地并入存储器控制器内的高速缓存控制器通过提供地址负载和地址提前信号来控制第二级高速缓冲存储器的操作。 突发SRAM能够识别更快的时钟脉冲，以及在地址负载和地址提前信号上断言的较短脉冲。 在更快的时钟信号的连续时钟周期期间，地址控制信号被断言然后被否定，使得脉冲串SRAM以与较低频率时钟信号对应的相同数据速率有效地工作。

公开(公告)号：US5805816A

公开(公告)日：1998-09-08

申请号：US788429

申请日：1997-01-28

Applicant: Jose J. Picazo, Jr. ,  Paul Kakul Lee ,  Robert P. Zager

Inventor： Jose J. Picazo, Jr. ,  Paul Kakul Lee ,  Robert P. Zager

IPC: G06F13/00 ,  H04L12/24 ,  H04L12/44 ,  H04L12/46 ,  H04L12/56 ,  H04L29/06

CPC classification number: H04L41/26 ,  H04L12/44 ,  H04L12/4616 ,  H04L12/462 ,  H04L12/4625 ,  H04L29/06 ,  H04L41/0213 ,  H04L41/046 ,  H04L49/351 ,  H04L49/90 ,  H04L49/901 ,  H04L63/0209 ,  H04L63/083 ,  H04L49/201 ,  H04L49/25 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/357 ,  H04L49/557

Abstract: A hub circuit with an integrated bridge circuit carried out in software including a switch for bypassing the bridge process such that the two bridged networks effectively become one network. An in-band management process in software is disclosed which receives and executes network management commands received as data packets from the LANs coupled to the integrated hub/bridge. Also, hardware and software to implement an isolate mode where data packets which would ordinarily be transferred by the bridge process are not transferred except in-band management packets are transferred to the in-band management process regardless of which network from which they arrived. Also disclosed, a packet switching machine having shared high-speed memory with multiple ports, one port coupled to a plurality of LAN controller chips coupled to individual LAN segments and an Ethernet microprocessor that sets up and manages a receive buffer for storing received packets and transferring pointers thereto to a main processor. The main processor is coupled to another port of the memory and analyzes received packets for bridging to other LAN segments or forwarding to an SNMP agent. The main microprocessor and the Ethernet processor coordinate to manage the utilization of storage locations in the shared memory. Another port is coupled to an uplink interface to higher speed backbone media such as FDDI, ATM etc. Speeds up to media rate are achieved by only moving pointers to packets around in memory as opposed to the data of the packets itself. A double password security feature is also implemented in some embodiments to prevent accidental or intentional tampering with system configuration settings.