公开(公告)号：US20140266122A1

公开(公告)日：2014-09-18

申请号：US13827666

申请日：2013-03-14

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Zhijie Zhu ,  Junxiao Chen ,  Bin Shao

IPC: H02M3/156

CPC classification number: H02M3/156 ,  H02M2003/1566

Abstract: Apparatus and methods for generating a drive signal of a switching signal are disclosed. A first circuit receives an oscillating reference signal, a first compensation signal, a second compensation signal, and a third compensation signal. The first compensation signal is indicative of an error between an output voltage of a power converter and a reference voltage. The second compensation signal is indicative of the error relative to a threshold. The third compensation signal is indicative of an output current of the power converter. The first circuit generates a comparison signal having a waveform including pulses having durations based at least partly on a combination of the periodic reference signal, the first compensation signal, the second compensation signal, and the third compensation signal. A second circuit receives a clock signal and the comparison signal and generates a drive signal for activation and deactivation of a driver transistor.

Abstract translation: 公开了用于产生开关信号的驱动信号的装置和方法。 第一电路接收振荡参考信号，第一补偿信号，第二补偿信号和第三补偿信号。 第一补偿信号表示功率转换器的输出电压与参考电压之间的误差。 第二补偿信号指示相对于阈值的误差。 第三补偿信号表示功率转换器的输出电流。 第一电路产生具有波形的比较信号，该波形包括至少部分地基于周期性参考信号，第一补偿信号，第二补偿信号和第三补偿信号的组合的具有持续时间的脉冲。 第二电路接收时钟信号和比较信号并产生用于驱动晶体管的激活和去激活的驱动信号。

公开(公告)号：US20140253176A1

公开(公告)日：2014-09-11

申请号：US13792835

申请日：2013-03-11

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Finbarr O'Leary ,  Michael Edward Bradley ,  Naiqian Ren ,  George R. Spalding ,  Nigel David Brooke

IPC: H03K5/22

CPC classification number: H03K5/22

Abstract: A ping pong comparator voltage monitoring circuit which includes first and second comparators having inputs connected to a voltage Vin to be monitored, and second inputs connected to first and second nodes, respectively. A multiplexer alternately couples the first and second comparator outputs to an output in response to a periodic control signal. A ground-referenced voltage Vref1 is provided at a third node and a voltage Vref2 referenced to Vref1 is at a fourth node. A hysteresis hyst1 is switchably connected between the third and first nodes, and a hysteresis hyst2 is switchably connected between the fourth and second nodes. Hyst1 and hyst2 are switched in when the mux output toggles due to a rising Vin, and are switched out when the mux output toggles due to a falling Vin.

Abstract translation: 乒乓比较器电压监视电路，其包括具有连接到要监视的电压Vin的输入的第一和第二比较器，以及分别连接到第一和第二节点的第二输入。 复用器响应于周期性控制信号将第一和第二比较器输出交替耦合到输出。 在第三节点处提供地参考电压Vref1，并且参考Vref1的电压Vref2在第四节点处。 迟滞hyst1可切换地连接在第三节点和第一节点之间，并且滞后hyst2可切换地连接在第四节点和第二节点之间。 当Mux输出由于Vin上升而切换时，Hyst1和hyst2被切换，并且当多路复用器输出由于Vin下降而切换时，Hyst1和hyst2被切换。

公开(公告)号：US20140253083A1

公开(公告)日：2014-09-11

申请号：US13791240

申请日：2013-03-08

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Bin Shao

IPC: G05F1/618

CPC classification number: H02M3/157 ,  H02M1/32 ,  H02M2001/0009 ,  H02M2001/0035

Abstract: In one aspect, this disclosure relates to a method of controlling current output from a switching regulator to a load via an inductor. Inductor current information can be sampled at a peak level, such as just before a transistor configured to cause current to flow through the inductor is turned off. The sampled inductor current can be compared with a reference current, and a current limit threshold can be adjusted based on the comparison. The output current of the switching regulator can be controlled based on a comparison of the current limit threshold with an indicator of current flowing through the inductor. This method can accurately and efficiently limit current in a switching regulator.

Abstract translation: 一方面，本公开涉及一种通过电感器控制从开关调节器到负载的电流输出的方法。 电感电流信息可以在峰值电平进行采样，例如在配置为使电流流过电感器的晶体管关闭之前。 可以将采样的电感电流与参考电流进行比较，并且可以基于比较来调整限流阈值。 可以基于电流限制阈值与流过电感器的电流指标的比较来控制开关稳压器的输出电流。 该方法可以准确有效地限制开关稳压器中的电流。

公开(公告)号：US08779532B2

公开(公告)日：2014-07-15

申请号：US13767214

申请日：2013-02-14

Applicant: Analog Devices Technology

Inventor： Alan J. O'Donnell ,  Michael J. Cusack ,  Rigan F. McGeehan ,  Garrett A. Griffin

IPC: H01L27/14

CPC classification number: B81B3/0018 ,  B81C1/0023 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/81

Abstract: Backside recesses in a base member host components, such as sensors or circuits, to allow closer proximity and efficient use of the surface space and internal volume of the base member. Recesses may include covers, caps, filters and lenses, and may be in communication with circuits on the frontside of the base member, or with circuits on an active backside cap. An array of recessed components may a form complete, compact sensor system.

Abstract translation: 基座构件中的背面凹部主体部件，例如传感器或电路，以允许更接近并有效地使用表面空间和基部构件的内部体积。 凹槽可以包括盖子，帽子，滤镜和透镜，并且可以与基座的前侧上的电路或主动背面盖上的电路连通。 一系列凹陷部件可以形成完整，紧凑的传感器系统。

公开(公告)号：US20140115195A1

公开(公告)日：2014-04-24

申请号：US14040367

申请日：2013-09-27

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Michael S. Allen ,  John L. Redford

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

Abstract translation: 根据一个示例实施例，公开了直接存储器存取（DMA）引擎和缓冲器。 向量缓冲器可以是可显式可编程的，并且可以包括用于重新排序非单位步幅矢量数据的高级逻辑。 示例MEMCPY指令可以向DMA缓冲器提供访问请求，其可以异步地服务请求。 按位保护设置在使用中的内存中，并在读取每个位时清零。

公开(公告)号：US10211662B2

公开(公告)日：2019-02-19

申请号：US14461003

申请日：2014-08-15

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yosef Stein ,  Roman Trogan ,  Haim Primo

IPC: H02J50/23 ,  H02J7/02 ,  H04W4/70 ,  H02J50/20 ,  H04W16/28 ,  H04W52/04 ,  H04B5/00 ,  H04B7/06 ,  H04W88/16 ,  H04W84/18 ,  H04W64/00

Abstract: A wireless charging network system is disclosed that includes wirelessly charged sensor nodes. The wireless network system can include a gateway node configured to aggregate data from sensor nodes within a coverage area of the gateway node. The gateway node is further configured to wirelessly transmit power to the sensor nodes using a beamformed signal, wherein the gateway node adjusts the beamformed signal to maximize wireless power transfer to sensor nodes within each sector of the coverage area. Location information can be used to adjust the beamformed signal. For example, in various embodiments, the gateway node includes a beamformer sector profile table that defines channel adaptive beam profiles for the beamformed signal for each sector of the coverage area. The gateway node can use location information to define the beam profiles.

公开(公告)号：US09912144B2

公开(公告)日：2018-03-06

申请号：US14477236

申请日：2014-09-04

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Trevor Clifford Caldwell ,  Corey Petersen ,  David Nelson Alldred ,  Hajime Shibata

IPC: H03M1/12 ,  H02H7/12 ,  H03M3/00

CPC classification number: H02H7/12 ,  H03M3/30 ,  H03M3/36 ,  H03M3/464 ,  H03M3/484

Abstract: Delta-sigma modulators do not handle overload well, and often become unstable if the input goes beyond the full-scale range of the modulator. To provide overload protection, an improved technique embeds an overload detector in the delta sigma modulator. When an overload condition is detected, coefficient(s) of the delta sigma modulator is adjusted to accommodate for the overloaded input. The improved technique advantageously allows the delta sigma modulator to handle overload gracefully without reset, and offers greater dynamic range at reduced resolution. Furthermore, the coefficient(s) of the delta sigma modulator can be adjusted in such a way to ensure the noise transfer function is not affected.

公开(公告)号：US09673696B2

公开(公告)日：2017-06-06

申请号：US14051702

申请日：2013-10-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yanfeng Lu ,  Bin Shao

IPC: H02M1/36 ,  H02M3/155 ,  H02M3/07

CPC classification number: H02M1/36 ,  H02M3/07 ,  H02M3/155 ,  H03K2217/0081

Abstract: At least one embodiment provides a method for a nanopower boost regulator to startup from an ultra-low-voltage (such as 0.3V˜0.5V) for energy harvesting applications. The method does not necessarily require a special process or any external components such as mechanical switches. The startup circuit can include an asynchronous boost circuit to charge up an output with stacked power NMOS transistors, a ring oscillator, and/or a charge pump, along with accompanying circuitry.

公开(公告)号：US09531262B2

公开(公告)日：2016-12-27

申请号：US14147228

申请日：2014-01-03

Applicant: Analog Devices Technology

Inventor： Roger Peppiette ,  Yanfeng Lu ,  Bin Shao ,  Linus Sheng

IPC: G05F1/10 ,  G05F3/02 ,  H02M3/07

CPC classification number: H02M3/073

Abstract: This application discusses, among other things apparatus and methods for a voltage boost circuit. In an example, a voltage boost circuit can include first and second inverters, sharing a first supply node, and sharing a second supply node, a first charge transfer capacitor, configured to couple a first clock signal to the first inverter output, a second charge transfer capacitor, configured to couple a second clock signal to the second inverter output, the second clock signal being out-of-phase with the first clock signal, a first gate drive capacitor, configured to couple the first clock signal to the second inverter input, and a second gate drive capacitor, configured to couple the second clock signal to the first inverter input.

Abstract translation: 本应用程序还讨论了升压电路的设备和方法。 在一个示例中，升压电路可以包括第一和第二反相器，共享第一电源节点，并共享第二电源节点，第一电荷转移电容器，被配置为将第一时钟信号耦合到第一反相器输出;第二充电 转移电容器，被配置为将第二时钟信号耦合到第二反相器输出，第二时钟信号与第一时钟信号异相;第一栅极驱动电容器，被配置为将第一时钟信号耦合到第二反相器输入 以及第二栅极驱动电容器，被配置为将所述第二时钟信号耦合到所述第一反相器输入。

公开(公告)号：US09411542B2

公开(公告)日：2016-08-09

申请号：US14187058

申请日：2014-02-21

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Gregory M. Yukna

IPC: G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/061 ,  G06F3/0637 ,  G06F13/1668 ,  Y02D10/14

Abstract: In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.

Abstract translation: 在一个示例中，本文公开了配置用于可中断原子排他存储器操作的处理器。 例如，负载独占（LDEX）可以后跟存储排他（STREX），两者一起形成一个原子。 为了方便及时处理中断，STREX操作分为两部分。 STREX_INIT不可中断，但具有确定的执行时间，因为它需要固定的时钟周期数。 STREX_INIT将值发送到内存总线。 之后是一个STREX_SYNC操作，轮询一个标志是否返回值可用。 STREX_SYNC是可中断的，并且公开了用于确定在从中断返回时是否已经破坏操作的原子性的方法。 如果原子性被破坏，则指令失败，而如果保留原子性，则指令完成。