公开(公告)号：US10985750B2

公开(公告)日：2021-04-20

申请号：US16885737

申请日：2020-05-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yohan Joly ,  Vincent Binet ,  Michel Cuenca

IPC: H03K17/56 ,  H03F3/45

Abstract: An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.

公开(公告)号：US10983937B2

公开(公告)日：2021-04-20

申请号：US16802116

申请日：2020-02-26

Applicant: STMicroelectronics SA ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Olivier Ferrand ,  Daniel Olson ,  Anis Ben Said ,  Emmanuel Ardichvili

IPC: G06F13/364 ,  G06F13/362 ,  G06F13/42

Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.

公开(公告)号：US10977365B2

公开(公告)日：2021-04-13

申请号：US16041077

申请日：2018-07-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Ibrahima Diop ,  Yanis Linge ,  Pierre-Yvan Liardet

IPC: G06F21/00 ,  G06F21/55 ,  G06F21/60 ,  G06F7/72 ,  H04L9/00 ,  G06F21/72

Abstract: An iterative calculation is performed on a first number and a second number, while protecting the iterative calculation against side-channel attacks. For each bit of the second number, successively, an iterative calculation routine of the bit of the second number is determined. The determination is made independent of a state of the bit. The determined iterative calculation routine of the bit is executed. A result of the iterative calculation is generated based on a result of the execution of the determined iterative calculation routine of a last bit of the second number.

公开(公告)号：US20210099162A1

公开(公告)日：2021-04-01

申请号：US17119865

申请日：2020-12-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Tramoni ,  Jimmy Fort

IPC: H03K4/50

Abstract: An embodiment provides a circuit of cyclic activation of an electronic function including a hysteresis comparator controlling the charge of a capacitive element powering the function.

公开(公告)号：US20210091015A1

公开(公告)日：2021-03-25

申请号：US17113645

申请日：2020-12-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L23/00

Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.

公开(公告)号：US10949572B2

公开(公告)日：2021-03-16

申请号：US16411819

申请日：2019-05-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas ,  Yanis Linge ,  Jimmy Fort

IPC: G06F21/75 ,  H04L9/00 ,  G06F30/327

Abstract: The supply voltage for a module of an integrated circuit managed to support protection against side channel attacks. Upon startup of the integrated circuit, one action from the following actions is selected in response to a command: supplying the module with the supply voltage having a fixed value that is selected from a plurality of predetermined values, or varying the value of the supply voltage in time with a pulsed signal.

公开(公告)号：US10937746B2

公开(公告)日：2021-03-02

申请号：US16549000

申请日：2019-08-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Pascal Fornara

IPC: H01L27/08 ,  H01L23/00 ,  G04F1/00 ,  H01L21/70 ,  H01L27/01 ,  H01L27/10

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunneling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

公开(公告)号：US20210057358A1

公开(公告)日：2021-02-25

申请号：US17091466

申请日：2020-11-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre SARAFIANOS ,  Abderrezak MARZAKI

IPC: H01L23/00 ,  G06F21/87 ,  H04L9/00 ,  H01L29/06 ,  G06F21/78 ,  G06F21/55

Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed to detect a DFA attack by fault injection into the integrated circuit.

公开(公告)号：US10931519B2

公开(公告)日：2021-02-23

申请号：US14971552

申请日：2015-12-16

Applicant: Proton World International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Olivier Van Nieuwenhuyze ,  Alexandre Charles

IPC: H04L12/24 ,  H04B5/00 ,  H04B5/02 ,  H04W4/80 ,  H04W76/14 ,  H04L29/08

Abstract: A method for configuring a first device for a near-field communication with a second device, wherein a peer-to-peer mode is selected if the second device draws the power supply of its circuits from a battery.

公开(公告)号：US10923484B2

公开(公告)日：2021-02-16

申请号：US16546002

申请日：2019-08-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: G11C17/16 ,  H01L27/112 ,  H01L23/58 ,  H01L23/528 ,  G11C17/18 ,  H01L23/525 ,  H01L23/522

Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.