公开(公告)号：US20160027774A1

公开(公告)日：2016-01-28

申请号：US14730826

申请日：2015-06-04

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard ,  Dalaf Ali

IPC: H01L27/08 ,  H01L23/528

CPC classification number: H01L27/0817 ,  H01L23/528 ,  H01L29/0834 ,  H01L29/747 ,  H01L2924/0002 ,  H01L2924/13033 ,  H01L2924/00

Abstract: A bidirectional switch formed in a substrate includes first and second main vertical thyristors in antiparallel connection. A third auxiliary vertical thyristor has a rear surface layer in common with the rear surface layer of the first thyristor. A peripheral region surrounds the thyristors and connects the rear surface layer to a layer of the same conductivity type of the third thyristor located on the other side of the substrate. A metallization connects the rear surfaces of the first and second thyristors. An insulating structure is located between the rear surface layer of the third thyristor and the metallization. The insulating structure extends under the periphery of the first thyristor. The insulating structure includes a region made of an insulating material and a complementary region made of a semiconductor material.

Abstract translation: 形成在衬底中的双向开关包括反并联连接的第一和第二主垂直晶闸管。 第三辅助垂直晶闸管具有与第一晶闸管的后表面层共同的后表面层。 周边区域围绕晶闸管并且将后表面层连接到位于基板另一侧上的与第三晶闸管相同的导电类型的层。 金属化连接第一和第二晶闸管的后表面。 绝缘结构位于第三晶闸管的后表面层与金属化之间。 绝缘结构在第一晶闸管的外围延伸。 绝缘结构包括由绝缘材料制成的区域和由半导体材料制成的互补区域。

公开(公告)号：US09172264B2

公开(公告)日：2015-10-27

申请号：US14013802

申请日：2013-08-29

Applicant: STMicroelectronics (TOURS) SAS

Inventor： Laurent Gonthier ,  Antoine Passal

IPC: H02J7/00 ,  E06B3/22 ,  E06B3/263 ,  E06B3/267 ,  E06B3/82 ,  E06B3/70

CPC classification number: H02J7/0052 ,  E06B3/22 ,  E06B3/26305 ,  E06B3/26345 ,  E06B3/267 ,  E06B3/822 ,  E06B2003/26312 ,  E06B2003/26316 ,  E06B2003/7076 ,  E06B2003/7082 ,  Y02A30/252 ,  Y02B80/28

Abstract: A circuit can be used for charging a capacitor with an AC voltage. In one embodiment, the circuit includes a capacitor coupled to be charged with the AC voltage. An adjustment is configured to adjust a capacitor charge speed according to a value of the AC voltage. The adjustment circuit includes at least one bipolar transistor coupled to receive a voltage at a base of the bipolar transistor. The voltage is a function of the value of the AC voltage.

Abstract translation: 电路可用于对具有交流电压的电容器充电。 在一个实施例中，电路包括耦合以对AC电压充电的电容器。 调整配置为根据交流电压的值调整电容器充电速度。 调节电路包括耦合以接收双极晶体管的基极处的电压的至少一个双极晶体管。 电压是交流电压值的函数。

公开(公告)号：US20150243437A1

公开(公告)日：2015-08-27

申请号：US14632981

申请日：2015-02-26

Applicant: STMicroelectronics (Tours) SAS

Inventor： Sylvain CHARLEY ,  Aline Noire

IPC: H01G2/00 ,  H01G17/00 ,  H01G7/00

CPC classification number: H03H7/38 ,  H01G4/38 ,  H01G7/06 ,  H03H5/12 ,  H03H2210/025 ,  H03H2210/033

Abstract: A capacitor having a capacitance settable by biasing, including: a series association of a plurality of first capacitive elements between two first terminals defining the capacitor electrodes; and two second terminals of application of bias voltages respectively connected, via resistive elements, to the opposite electrodes of each of the first capacitive elements.

Abstract translation: 一种电容器，其具有通过偏置设定的电容，包括：在限定所述电容器电极的两个第一端子之间的多个第一电容元件的串联关联; 以及施加偏置电压的两个第二端子分别通过电阻元件连接到每个第一电容元件的相对电极。

公开(公告)号：US20150221782A1

公开(公告)日：2015-08-06

申请号：US14607577

申请日：2015-01-28

Applicant: STMICROELECTRONICS (TOURS) SAS ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  UNIVERSITE FRANCOIS RABELAIS

Inventor： Arnaud YVON ,  Daniel ALQUIER ,  Yvon Cordier

IPC: H01L29/872 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/872 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/66212

Abstract: A Schottky diode may include a semiconductor substrate having first and second opposing surfaces, and a buffer layer over the first surface of the semiconductor substrate. The Schottky diode may include a first doped GaN layer over the buffer layer and having first and second opposing surfaces, the second surface of the first doped GaN layer being adjacent the buffer layer, and a second doped GaN layer over the second surface of the first doped GaN layer and having a dopant concentration level less than a dopant concentration level of the first doped GaN layer. The buffer layer, the first doped GaN layer, and the second doped GaN layer may define an opening. The Schottky diode may include a first metallization layer being coupled to the semiconductor substrate and to the first surface of the first doped GaN layer and being in the opening.

Abstract translation: 肖特基二极管可以包括具有第一和第二相对表面的半导体衬底和在半导体衬底的第一表面上的缓冲层。 肖特基二极管可以包括在缓冲层上的第一掺杂GaN层，并且具有第一和第二相对表面，第一掺杂GaN层的第二表面与缓冲层相邻，第二掺杂GaN层在第一 并且具有小于第一掺杂GaN层的掺杂剂浓度水平的掺杂剂浓度水平。 缓冲层，第一掺杂GaN层和第二掺杂GaN层可以限定开口。 肖特基二极管可以包括耦合到半导体衬底和第一掺杂GaN层的第一表面并处于开口中的第一金属化层。

公开(公告)号：US08994065B2

公开(公告)日：2015-03-31

申请号：US13901494

申请日：2013-05-23

Applicant: STMicroelectronics (Tours) SAS ,  Universite Francois Rabelais

Inventor： Samuel Menard ,  Gaël Gautier

IPC: H01L29/747 ,  H01L29/74 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/74 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/66386 ,  H01L29/747

Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.

Abstract translation: 一种垂直功率分量，包括：第一导电类型的硅衬底; 在支撑单个电极的基板的下表面侧，具有第二导电类型的下层; 并且在支撑导电电极和栅电极的基板的上表面侧，具有第二导电类型的上部区域，其中，所述元件周边在下表面上包括穿入基板的多孔硅绝缘环 下降到比下层更深的深度。

公开(公告)号：US08989416B2

公开(公告)日：2015-03-24

申请号：US14091824

申请日：2013-11-27

Applicant: STMicroelectronics (Tours) SAS

Inventor： Frédéric Cantin

IPC: H04R25/00 ,  H01M10/46

CPC classification number: H04R25/55 ,  H01M10/46 ,  H01M2220/30 ,  H04R2225/023 ,  H04R2225/31

Abstract: An object containing electronic circuits and a rechargeable cell, wherein the cell is arranged close to a surface of the object, a charge coil being shiftable with respect to the cell between an operating position where it is arranged around the cell and a recharge position where it is axially offset with respect to the cell.

Abstract translation: 一种包含电子电路和可充电电池的物体，其中所述电池靠近所述物体的表面布置，所述电荷线圈可相对于所述电池在围绕所述电池的布置的操作位置和所述电池的充电位置之间移动， 相对于电池轴向偏移。

公开(公告)号：US20140217462A1

公开(公告)日：2014-08-07

申请号：US13762288

申请日：2013-02-07

Applicant: STMICROELECTRONICS (TOURS) SAS ,  UNIVERSITE FRANCOIS RABELAIS

Inventor： Samuel Menard ,  Gaël Gautier

IPC: H01L29/74 ,  H01L21/22

CPC classification number: H01L29/7424 ,  H01L29/0619 ,  H01L29/167 ,  H01L29/66386 ,  H01L29/747

Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.

Abstract translation: 一种高电压垂直功率元件，包括第一导电类型的硅衬底和从硅衬底的上表面延伸到硅衬底中的第二导电类型的第一半导体层，其中所述元件周边包括：多孔硅 环从上表面延伸到深度比第一层深的硅衬底; 以及从硅表面的下表面延伸到多孔硅环的第二导电类型的掺杂环。

公开(公告)号：US08648992B2

公开(公告)日：2014-02-11

申请号：US13938593

申请日：2013-07-10

Applicant: Mitsubishi Materials Corporation ,  STMicroelectronics(Tours) SAS

Inventor： Hideaki Sakurai ,  Toshiaki Watanabe ,  Nobuyuki Soyama ,  Guillaume Guegan

IPC: G02F1/1343

CPC classification number: H01L28/60 ,  B82Y30/00 ,  C04B35/4682 ,  C04B2235/3213 ,  C04B2235/441 ,  C04B2235/781 ,  C04B2235/785 ,  C04B2235/787 ,  H01G4/01 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02197 ,  H01L21/02282 ,  H01L28/55 ,  H01L28/65

Abstract: A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.

Abstract translation: 薄膜电容器的特征在于形成下电极，在不施加温度大于300℃的退火工艺的情况下将组合物涂覆在下电极上，在从环境温度至500℃的范围内的预定温度下干燥 并在500〜800℃的范围内的预定温度下煅烧并高于干燥温度。 从涂覆到煅烧的过程进行从涂覆到煅烧一次或至少两次的过程，或者从涂覆到干燥的过程进行至少两次，然后进行一次煅烧。 在第一次煅烧后形成的电介质薄膜的厚度为20〜600nm。 初始煅烧步骤后形成的下部电极的厚度与电介质薄膜的厚度之比（下部电极的厚度/电介质薄膜的厚度）优选在0.10〜15.0的范围内。

公开(公告)号：US20130257559A1

公开(公告)日：2013-10-03

申请号：US13907455

申请日：2013-05-31

Applicant: STMicroelectronics (Tours) SAS

Inventor： François Dupont ,  Hilal Ezzeddine ,  Sylvain Charley

IPC: H01P5/18

CPC classification number: H01P5/18 ,  H01P5/184

Abstract: A distributed-line directional coupler including: a first conductive line between first and second ports intended to convey a signal to be transmitted; and a second conductive line, coupled to the first one, between third and fourth ports, the second line being interrupted approximately at its middle, the two intermediary ends being connected to attenuators.

公开(公告)号：US20130178017A1

公开(公告)日：2013-07-11

申请号：US13783529

申请日：2013-03-04

Applicant: STMicroelectronics (Tours) SAS

Inventor： Vincent Jarry ,  Patrick Hougron ,  Dominique Touzet ,  José Mendez

IPC: H01L21/683 ,  H01L21/78

CPC classification number: H01L21/683 ,  H01L21/67132 ,  H01L21/78 ,  Y10T29/41 ,  Y10T83/02 ,  Y10T225/393

Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.

Abstract translation: 一种用于从半导体晶片制造半导体芯片的方法，包括以下步骤：在第一支撑框架上紧固外部尺寸小于第一框架的外部尺寸并大于第一框架的内部尺寸的第二支撑框架 ; 将晶片布置在在第二框架上延伸的膜的表面上; 通过使用能够接收第一帧的设备进行晶片处理操作; 将第二框架与第一框架分离并移除第一框架; 并通过使用能够接收第二帧的设备进行晶片处理操作。