公开(公告)号：US08962478B1

公开(公告)日：2015-02-24

申请号：US14079305

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Kunaljeet Tanwar

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include forming a cavity in a SiO-based ILD; conformally forming a doped TaN layer in the cavity and over the ILD; conformally forming a Ru layer on the doped TaN layer; depositing Cu over the Ru layer and filling the cavity; planarizing the Cu, Ru layer, and doped TaN layer down to an upper surface of the ILD; forming a dielectric cap over the Cu, Ru layer, and doped TaN layer; and filling spaces formed between the dielectric cap and the doped TaN layer.

Abstract translation: 提供了形成与Cu互连结构的Ru层相邻的掺杂TaN Cu势垒的方法和所得到的器件。 实施例包括在SiO基ILD中形成空腔; 在空腔中并在ILD上保形地形成掺杂的TaN层; 在掺杂的TaN层上保形地形成Ru层; 在Ru层上沉积Cu并填充空腔; 将Cu，Ru层和掺杂的TaN层平坦化到ILD的上表面; 在Cu，Ru层和掺杂的TaN层上形成电介质盖; 以及形成在电介质盖和掺杂的TaN层之间的填充空间。

公开(公告)号：US08907483B2

公开(公告)日：2014-12-09

申请号：US13648433

申请日：2012-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Larry Zhao ,  Ming He ,  Xunyuan Zhang ,  Sean Xuan Lin

IPC: H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

Abstract translation: 提供了一种用于形成半导体器件的方法。 通常，通过在金属层上设置金属层，覆盖层和覆盖层上的超低k层来形成器件。 然后通过超低k层和盖层形成通孔。 一旦形成通孔，就可以选择性地将阻挡层（例如钴（Co），钽（Ta），钴 - 钨 - 磷化物（CoWP）或其它能够用作铜（CU）扩散阻挡层的金属） 通孔的底面。 然后将衬垫层（例如锰（MN）或铝（AL））施加到通孔的一组侧壁。 然后可以用随后的金属层（具有或不具有种子层）填充通孔，然后可以进一步处理（例如，退火）该器件。

公开(公告)号：US20140357079A1

公开(公告)日：2014-12-04

申请号：US13905271

申请日：2013-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Xiuyu Cai

IPC: H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/76804

Abstract: One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material, forming a layer of sacrificial material so as to overfill the cavity, performing at least one planarization process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity.

Abstract translation: 本文公开的一种说明性方法包括在导电结构之上形成至少一层绝缘材料，形成由绝缘材料层上方的金属构成的图案化硬掩模，执行至少一个蚀刻工艺以在绝缘材料层中限定空腔 形成牺牲材料层以便过度填充空腔，执行至少一个平坦化处理以去除牺牲材料层和图案化的硬掩模的一部分，同时将牺牲材料层的剩余部分留在空腔内， 以及去除位于腔内的牺牲材料层的剩余部分。

公开(公告)号：US20140357078A1

公开(公告)日：2014-12-04

申请号：US13904567

申请日：2013-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Xiuyu Cai ,  Kunaljeet Tanwar

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/32134 ,  H01L2221/1063

Abstract: One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material that exposes at least a portion of a conductive structure, forming a layer of sacrificial material that covers the exposed portion of the conductive structure, with the layer of sacrificial material in position, performing at least one second etching process to remove the patterned hard mask while leaving the layer of sacrificial material in position within the cavity, and removing the layer of sacrificial material positioned within the cavity.

Abstract translation: 本文公开的一种说明性方法包括在导电结构之上形成至少一层绝缘材料，形成由绝缘材料层上方的金属构成的图案化硬掩模，执行至少一个蚀刻工艺以在绝缘材料层中限定空腔 其暴露导电结构的至少一部分，形成覆盖导电结构的暴露部分的牺牲材料层，其中牺牲材料层在适当位置，执行至少一个第二蚀刻工艺以移除图案化的硬掩模，同时 将牺牲材料层留在空腔内的适当位置，以及去除位于空腔内的牺牲材料层。

公开(公告)号：US08859419B2

公开(公告)日：2014-10-14

申请号：US13757338

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/58 ,  H01L29/04 ,  H01L31/036 ,  H01L29/06 ,  H01L31/0352 ,  H01L23/22 ,  H01L23/24 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中形成阻挡层，在阻挡层上形成铜基种子层，将至少一部分铜基 种子层形成铜基氮化物层，在铜基氮化物层上沉积大块铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺，以去除位于沟槽之外的多余材料 / via，从而限定铜基导电结构。 本文公开的装置包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和层之间的铜基硅或氮化锗层 的绝缘材料。

公开(公告)号：US20140110798A1

公开(公告)日：2014-04-24

申请号：US13656794

申请日：2012-10-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Xunyuan Zhang

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L29/4991 ,  H01L21/7682 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78

Abstract: One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer.

Abstract translation: 本文公开的一种方法包括形成邻近牺牲栅极结构的至少一个牺牲侧壁间隔物，所述牺牲栅极结构形成在半导体衬底上方，去除牺牲栅极结构的至少一部分，从而限定由牺牲隔离物横向限定的栅极腔， 在栅极腔中形成替代栅极结构，去除牺牲隔离物，从而限定邻近置换栅极结构的间隔空腔，并在间隔空腔中形成低k隔离物。 本文公开的新型器件包括位于半导体衬底上方的栅极结构，其中栅绝缘层具有相对于衬底的上表面基本上垂直取向的两个直立部分。 该装置还包括邻近栅极绝缘层的垂直取向的竖立部分的低k侧壁间隔件。

公开(公告)号：US20140021615A1

公开(公告)日：2014-01-23

申请号：US13770026

申请日：2013-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC: H01L23/532 ,  H01L23/538 ,  H01L21/02

CPC classification number: H01L23/53209 ,  H01L21/02697 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5384 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is generally directed to multi-layer barrier layer stacks for interconnect structures that may be used to reduce mechanical stress levels between the interconnect structure and a dielectric material layer in which the interconnect structure is formed. One illustrative method disclosed herein includes forming a recess in a dielectric layer of a substrate and forming an adhesion barrier layer including an alloy of tantalum and at least one transition metal other than tantalum to line the recess, wherein forming the adhesion barrier layer includes creating a first stress level across a first interface between the adhesion barrier layer and the dielectric layer. The method also includes forming a stress-reducing barrier layer including tantalum over the adhesion barrier layer, wherein the stress-reducing barrier layer reduces the first stress level to a second stress level less than the first stress level, and filling the recess with a fill layer.

Abstract translation: 本公开通常涉及用于互连结构的多层势垒层堆叠，其可用于减小互连结构与其中形成互连结构的介电材料层之间的机械应力水平。 本文公开的一种说明性方法包括在基底的电介质层中形成凹陷，并形成包括钽和至少一种不同于钽的过渡金属的合金的粘合阻挡层，以使凹槽成直线，其中形成粘合阻挡层包括形成 在粘合阻挡层和电介质层之间的第一界面上的第一应力水平。 该方法还包括在粘合阻挡层上形成包括钽的应力减小阻挡层，其中减小应力的阻挡层将第一应力水平降低到小于第一应力水平的第二应力水平，并且用填充物填充凹部 层。

公开(公告)号：US20130241062A1

公开(公告)日：2013-09-19

申请号：US13849415

申请日：2013-03-22

Applicant: GLOBALFOUNDRIES INC

Inventor： Errol T. Ryan ,  Xunyuan Zhang

IPC: H01L23/535

CPC classification number: H01L23/535 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.

Abstract translation: 提供集成电路，用于凹入衬底内的嵌入式铜特征的工艺，以及用于使集成电路的层间电介质衬底内的嵌入式铜互连凹陷的工艺。 在一个实施例中，在诸如层间电介质基板的衬底内嵌入诸如嵌入式铜互连的嵌入式铜特征的方法包括提供其中布置有嵌入式铜特征的衬底。 嵌入的铜特征具有暴露的表面，并且衬底具有与嵌入的铜特征的暴露表面相邻的衬底表面。 嵌入的铜特征的暴露表面被氮化以在嵌入的铜特征中形成一层氮化铜。 从嵌入的铜特征中选择性地蚀刻氮化铜以将嵌入的铜特征凹入到衬底内。

公开(公告)号：US10262892B2

公开(公告)日：2019-04-16

申请号：US15345882

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.

公开(公告)号：US10211147B2

公开(公告)日：2019-02-19

申请号：US15643032

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Chanro Park ,  Lei Sun ,  Yi Qi ,  Roderick Augur

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. A layer stack is deposited that includes a first conductor layer, a second conductor layer, and a third conductor layer. The layer stack is patterned to define a first electrode of the MIM capacitor from the first conductor layer, a second electrode of the MIM capacitor from the second conductor layer, and a third electrode of the MIM capacitor from the third conductor layer. A via opening is formed that extends vertically through the layer stack. The first electrode is recessed relative to the second electrode to define a cavity that is laterally offset from the via opening. A dielectric inner spacer is formed in the cavity. A conductive via is formed in the first via opening after the dielectric inner spacer is formed.