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    INTEGRATED CIRCUIT SELF ALIGNED 3D MEMORY ARRAY AND MANUFACTURING METHOD
    111.
    发明申请
    INTEGRATED CIRCUIT SELF ALIGNED 3D MEMORY ARRAY AND MANUFACTURING METHOD 有权
    集成电路自对准3D存储阵列和制造方法

    公开(公告)号：US20100226195A1

    公开(公告)日：2010-09-09

    申请号：US12692798

    申请日：2010-01-25

    Applicant: Hang-Ting Lue

    Inventor： Hang-Ting Lue

    IPC: G11C8/10 ,  H01L23/525 ,  H01L29/792 ,  H01L21/82

    CPC classification number: G11C5/06 ,  G11C5/02 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.

    Abstract translation: 3D存储器件包括多个由绝缘材料隔开的多条导电材料形式的脊状叠层，排列成可通过解码电路耦合到读出放大器的位线。 导电材料条具有在脊形叠层的侧面上的侧表面。 布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。 导线符合堆叠的表面。 存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。 存储器元件是可编程的，如抗熔丝或电荷捕获结构。 3D存储器仅使用两层用于多层的关键掩模。

    Method and Apparatus for Programming Nonvolatile Memory
    113.
    发明申请
    Method and Apparatus for Programming Nonvolatile Memory 有权
    用于编程非易失性存储器的方法和装置

    公开(公告)号：US20100157686A1

    公开(公告)日：2010-06-24

    申请号：US12715996

    申请日：2010-03-02

    Applicant: Hang-Ting Lue ,  Tzu Hsuan Hsu

    Inventor： Hang-Ting Lue ,  Tzu Hsuan Hsu

    IPC: G11C16/04

    CPC classification number: G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

    Abstract: A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected memory cell of the memory array with data. The series of programming bias arrangements include multiple sets of changing gate voltage values to the memory cells.

    Abstract translation: 非易失性存储器具有执行编程操作的逻辑，其控制一系列编程偏置布置，以用数据对存储器阵列的至少一个选定存储单元进行编程。 一系列编程偏置布置包括对存储器单元的多组改变栅极电压值。

    Methods of operating p-channel non-volatile memory devices
    115.
    发明授权
    Methods of operating p-channel non-volatile memory devices 有权
    操作p通道非易失性存储器件的方法

    公开(公告)号：US07636257B2

    公开(公告)日：2009-12-22

    申请号：US11417939

    申请日：2006-05-04

    Applicant: Hang-Ting Lue

    Inventor： Hang-Ting Lue

    IPC: G11C11/34

    CPC classification number: G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11568

    Abstract: Methods of operating non-volatile memory devices are described. The memory devices comprise memory cells having an n-type semiconductor substrate and p-type source and drain regions disposed below a surface of the substrate and separated by a channel region. A tunneling dielectric layer is disposed above the channel region. A charge storage layer is disposed above the tunneling dielectric layer. An upper insulating layer is disposed above the charge storage layer, and a gate is disposed above the upper insulating multi-layer structure. A positive bias is applied to a word lines of the memory device in a selected memory cell and a negative bias is applied to a bit line in the selected cell.

    Abstract translation: 描述操作非易失性存储器件的方法。 存储器件包括具有n型半导体衬底的存储器单元和设置在衬底的表面下方并由沟道区分隔开的p型源极和漏极区域的存储器单元。 隧道介电层设置在沟道区域的上方。 电荷存储层设置在隧道电介质层的上方。 上部绝缘层设置在电荷存储层上方，栅极设置在上绝缘多层结构的上方。 对所选存储单元中的存储器件的字线施加正偏压，并将负偏压施加到所选择的单元中的位线。

    Method of manufacturing a non-volatile memory device
    117.
    发明申请
    Method of manufacturing a non-volatile memory device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US20090075466A1

    公开(公告)日：2009-03-19

    申请号：US12216679

    申请日：2008-07-09

    Applicant: Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    Inventor： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC: H01L21/3205

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/115

    Abstract: A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

    Abstract translation: 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅极上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

    Method and Apparatus for Programming Nonvolatile Memory
    118.
    发明申请
    Method and Apparatus for Programming Nonvolatile Memory 有权
    用于编程非易失性存储器的方法和装置

    公开(公告)号：US20090046506A1

    公开(公告)日：2009-02-19

    申请号：US12188499

    申请日：2008-08-08

    Applicant: Hang-Ting Lue ,  Tzu Hsuan Hsu

    Inventor： Hang-Ting Lue ,  Tzu Hsuan Hsu

    IPC: G11C16/12

    CPC classification number: G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

    Abstract: A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected memory cell of the memory array with data. The series of programming bias arrangements include multiple sets of changing gate voltage values to the memory cells.

    Abstract translation: 非易失性存储器具有执行编程操作的逻辑，其控制一系列编程偏置布置，以用数据对存储器阵列的至少一个选定存储单元进行编程。 一系列编程偏置布置包括对存储器单元的多组改变栅极电压值。

    Operating method of non-volatile memory device
    119.
    发明授权
    Operating method of non-volatile memory device 有权
    非易失性存储器件的操作方法

    公开(公告)号：US07463530B2

    公开(公告)日：2008-12-09

    申请号：US11554455

    申请日：2006-10-30

    Applicant: Hang-Ting Lue ,  Erh-Kun Lai ,  Szu-Yu Wang

    Inventor： Hang-Ting Lue ,  Erh-Kun Lai ,  Szu-Yu Wang

    IPC: G11C11/34

    CPC classification number: H01L29/42324 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513

    Abstract: An operating method of non-volatile memory device is provided. The device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel region, a charge storage layer disposed on the insulating layer, a multi-layer tunneling dielectric structure on the charge storage layer, and a gate disposed on the multi-layer tunneling dielectric structure. A negative bias is supplied to the gate to inject electrons into the charge storage layer through the multi-layer tunneling dielectric structure by −FN tunneling so that the threshold voltage of the device is increased. A positive bias is supplied to the gate to inject holes into the charge storage layer through the multi-layer tunneling dielectric structure by +FN tunneling so that the threshold voltage of the device is decreased.

    Abstract translation: 提供了一种非易失性存储器件的操作方法。 该器件包括具有半导体衬底，堆叠层以及设置在衬底的表面下方并由沟道区分隔开的源极和漏极区的存储单元。 堆叠层包括设置在沟道区上的绝缘层，设置在绝缘层上的电荷存储层，电荷存储层上的多层隧道电介质结构，以及设置在多层隧道电介质结构上的栅极。 向栅极提供负偏压，通过多沟道介质结构通过-FN隧穿将电子注入电荷存储层，从而增加器件的阈值电压。 向栅极提供正偏压，以通过+ FN隧穿通过多层隧道电介质结构将空穴注入电荷存储层，使得器件的阈值电压降低。

    MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME
    120.
    发明申请
    MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME 有权
    存储单元及其制造方法

    公开(公告)号：US20080290391A1

    公开(公告)日：2008-11-27

    申请号：US11958134

    申请日：2007-12-17

    Applicant: Tzu-Hsuan Hsu ,  Hang-Ting Lue

    Inventor： Tzu-Hsuan Hsu ,  Hang-Ting Lue

    IPC: H01L21/8247 ,  H01L27/115 ,  G11C11/34

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66833 ,  H01L29/792

    Abstract: The invention provides a memory cell. The memory cell is disposed on a substrate and comprises a plurality of isolation structures defining at least a fin structure in the substrate. Further, the surface of the fin structure is higher than the surface of the isolation structure. The memory cell comprises a doped region, a gate, a charge trapping structure and a source/drain region. The doped region is located in a top of the fin structure and near a surface of the top of the fin structure and the doped region has a first conductive type. The gate is disposed on the substrate and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The source/drain region with a second conductive type is disposed in the fin structures exposed by the gate and the first conductive type is different from the second conductive type.

    Abstract translation: 本发明提供了一种存储单元。 存储单元设置在基板上并且包括在基板中限定至少鳍结构的多个隔离结构。 此外，翅片结构的表面高于隔离结构的表面。 存储单元包括掺杂区域，栅极，电荷俘获结构和源极/漏极区域。 掺杂区域位于鳍结构的顶部并且在鳍结构的顶部的表面附近，并且掺杂区域具有第一导电类型。 栅极设置在基板上并跨越翅片结构。 电荷捕获结构设置在栅极和鳍结构之间。 具有第二导电类型的源极/漏极区域设置在由栅极暴露的鳍状结构中，并且第一导电类型不同于第二导电类型。

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