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    Semiconductor memory array having sublithographic spacing between adjacement trenches and method for making the same
    111.
    发明授权
    Semiconductor memory array having sublithographic spacing between adjacement trenches and method for making the same 失效
    具有辅助沟槽之间的亚光刻间隔的半导体存储器阵列及其制造方法

    公开(公告)号：US6034877A

    公开(公告)日：2000-03-07

    申请号：US93902

    申请日：1998-06-08

    申请人： Gary Bela Bronner ,  Jack Allan Mandelman ,  Donald James Samuels

    发明人： Gary Bela Bronner ,  Jack Allan Mandelman ,  Donald James Samuels

    IPC分类号： H01L21/8242 ,  G11C11/24

    CPC分类号： H01L27/1087

    摘要： Disclosed herein is an arrangement of memory cells in which the spacing between back-to-back trench capacitors is defined at less than 1 F spacing. A pure phase edge mask is used to define such trench patterns having less than 1 F spacing. The reduction in the trench-to-trench spacing results in increased separation between the trench and the near edge of the gate conductor. This increase in the trench to gate conductor spacing, in turn, permits the channel doping concentration to be decreased, with a corresponding increase in ON current to be realized. In alternative embodiments, a pure phase edge mask or a blocked phase edge mask can be used to define trench patterns in which the width of trenches is increased to form storage capacitors having higher capacitance. In such embodiments, the spacing between back-to-back trenches can be reduced, such that the total separation between the outer edges of adjacent trenches is maintained at about 3 F or less.

    摘要翻译： 本文公开了一种存储单元的布置，其中背对背沟槽电容器之间的间隔被限定在小于1F的间隔。 使用纯相边缘掩模来限定具有小于1F间距的这种沟槽图案。 沟槽间距的减小导致沟槽和栅极导体的近边缘之间的间隔增加。 沟槽与栅极导体间隔的增加又使得沟道掺杂浓度降低，同时实现ON电流的相应增加。 在替代实施例中，可以使用纯相边缘掩模或阻挡相边缘掩模来限定其中沟槽宽度增加以形成具有较高电容的存储电容器的沟槽图案。 在这样的实施例中，可以减小背对背沟槽之间的间隔，使得相邻沟槽的外边缘之间的总间隔保持在约3°F或更小。

    Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods
    115.
    发明授权
    Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods 有权
    使用多孔层形成绝缘体上半导体结构的方法和通过这些方法形成的半导体结构的方法

    公开(公告)号：US07928436B2

    公开(公告)日：2011-04-19

    申请号：US12120455

    申请日：2008-05-14

    申请人： Kangguo Cheng ,  Brian Joseph Greene ,  Jack Allan Mandelman

    发明人： Kangguo Cheng ,  Brian Joseph Greene ,  Jack Allan Mandelman

    IPC分类号： H01L29/04 ,  H01L29/10

    CPC分类号： H01L21/76251 ,  H01L21/76245 ,  Y10S438/933

    摘要： A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.

    摘要翻译： 一种半导体结构，其包括单晶含锗层，优选基本上纯的锗，衬底和将锗含量层与衬底分离的掩埋绝缘体层。 在基板上形成可以是多孔硅的多孔层，在多孔硅层上形成含锗层。 多孔层可以转化成一层氧化物，这提供了埋层绝缘体层。 或者，含锗层可以从多孔层转移到另一衬底上的绝缘层。 在转移之后，绝缘层被埋在后面的衬底和含锗层之间。

    Well isolation trenches (WIT) for CMOS devices
    118.
    发明授权
    Well isolation trenches (WIT) for CMOS devices 失效
    用于CMOS器件的隔离沟槽（WIT）

    公开(公告)号：US07737504B2

    公开(公告)日：2010-06-15

    申请号：US11759981

    申请日：2007-06-08

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L29/772

    CPC分类号： H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

    摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

    摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。