公开(公告)号：US10944399B2

公开(公告)日：2021-03-09

申请号：US15779074

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Patrick Morrow ,  Anurag Chaudhry

IPC: H03K19/00 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H03K19/18

Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

公开(公告)号：US10910556B2

公开(公告)日：2021-02-02

申请号：US16081001

申请日：2016-03-29

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Ravi Pillarisetty ,  Uygar E. Avci

IPC: H01L43/10 ,  G11B5/73 ,  G11C11/16 ,  H01F10/32 ,  G11B5/72

Abstract: Described is an apparatus which comprises: a heat spreading layer; a first transition metal layer adjacent to the heat spreading layer; and a magnetic recording layer adjacent to the first transition metal layer. Described is an apparatus which comprises: a first electrode; a magnetic junction having a free magnet; and one or more layers of Jahn-Teller material adjacent to the first electrode and the free magnet of the magnetic junction.

公开(公告)号：US10832761B2

公开(公告)日：2020-11-10

申请号：US16732951

申请日：2020-01-02

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G11C11/00 ,  G11C11/412 ,  G11C8/16 ,  G11C11/419 ,  H01L27/11 ,  G11C11/22

Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

公开(公告)号：US10777250B2

公开(公告)日：2020-09-15

申请号：US16144896

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Huichu Liu ,  Dileep J. Kurian ,  Uygar E. Avci ,  Tanay Karnik ,  Ian A. Young

IPC: G11C11/22 ,  G06F1/3234 ,  G11C11/413 ,  G11C14/00

Abstract: Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.

公开(公告)号：US20200286984A1

公开(公告)日：2020-09-10

申请号：US16296035

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Ashish Verma Penumatcha ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L49/02 ,  H01L27/108 ,  H01L27/11507

Abstract: Disclosed herein are capacitors with ferroelectric or antiferroelectric (FE/AFE) material and dielectric material, as well as related methods and devices. In some embodiments, a capacitor may include two electrodes, a layer of FE/AFE material between the electrodes, and a layer of dielectric material between the electrodes.

公开(公告)号：US20200286685A1

公开(公告)日：2020-09-10

申请号：US16294811

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L49/02 ,  H01L27/108

Abstract: Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.

公开(公告)号：US10734378B2

公开(公告)日：2020-08-04

申请号：US16080914

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49

Abstract: One embodiment provides an apparatus. The apparatus includes a first transistor and a second transistor. The first transistor includes a first drain, a first source coupled to the first drain by a first channel, and a first gate stack comprising a plurality of layers. The second transistor includes a second drain, a second source coupled to the second drain by a second channel, and a second gate stack comprising a plurality of layers. Each gate stack includes a work function material layer to optimize a threshold voltage variation between the transistors.

公开(公告)号：US20190334010A1

公开(公告)日：2019-10-31

申请号：US15751104

申请日：2015-09-11

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11585

Abstract: Described is an apparatus which comprises a transistor including: a layer of ferroelectric material; a layer of insulating material; and an oxide layer or a metal layer sandwiched between the layer of ferroelectric material and the layer of insulating material, wherein thickness of the ferroelectric material is less than thickness of the layer of insulating material; and a driver coupled to the transistor. Described is an apparatus which comprises: a transistor including: a first oxide layer of High-K material; a second oxide layer; and a layer of nanocrystals sandwiched between the first and second oxide layers, wherein thickness of first oxide layer is greater than thickness of the second oxide layer; and a driver coupled to the transistor.

公开(公告)号：US20190273087A1

公开(公告)日：2019-09-05

申请号：US16347085

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/1159 ,  G11C11/22 ,  H01L29/78

Abstract: Described herein are ferroelectric memory cells and corresponding methods and devices. For example, in some embodiments, a ferroelectric memory cell disclosed herein includes one access transistor and one ferroelectric transistor (1T-1FE-FET cell). The access transistor is coupled to the ferroelectric transistor by sharing its source/drain terminal with that of the ferroelectric transistor and is used for both READ and WRITE access to the ferroelectric transistor.

公开(公告)号：US10355005B2

公开(公告)日：2019-07-16

申请号：US15576269

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young ,  Stephen M. Ramey

IPC: H01L27/11521 ,  G11C16/04 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L27/11519 ,  H01L27/11558 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11526 ,  H01L29/66 ,  H01L21/762 ,  H01L27/02 ,  H01L29/06

Abstract: Embodiments of the present disclosure provide techniques and configurations for semi-volatile embedded memory with between-fin floating gates. In one embodiment, an apparatus includes a semiconductor substrate and a floating-gate memory structure formed on the semiconductor substrate including a bitcell having first, second, and third fin structures extending from the substrate, an oxide layer disposed between the first and second fin structures and between the second and third fin structures, a gate of a first transistor disposed on the oxide layer and coupled with and extending over a top of the first fin structure, and a floating gate of a second transistor disposed on the oxide layer between the second and third fin structures. Other embodiments may be described and/or claimed.