公开(公告)号：US20220165944A1

公开(公告)日：2022-05-26

申请号：US16949909

申请日：2020-11-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Carl Radens ,  Ruilong Xie ,  Juntao Li

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A non-volatile memory structure, and methods of manufacture, which may include a first memory element and a second memory element between a first terminal and a second terminal. The first memory element and the second memory element may be in parallel with each other between the first and second terminal. This may enable the hybrid non-volatile memory structure to store values as a combination of the conductance for each memory element, thereby enabling better tuning of set and reset conductance parameters.

公开(公告)号：US11175844B1

公开(公告)日：2021-11-16

申请号：US15929618

申请日：2020-05-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashish Ranjan ,  Arvind Kumar ,  Carl Radens

IPC: G06F13/00 ,  G06F3/06 ,  G06N3/04

Abstract: In a deep neural network (DNN), weights are defined that represent a strength of connections between different neurons of the DNN and activations are defined that represent an output produced by a neuron after passing through an activation function of receiving an input and producing an output based on some threshold value. The weight traffic associated with a hybrid memory therefore is distinguished from the activation traffic to the hybrid memory, and one or more data structures may be dynamically allocated in the hybrid memory according to the weights and activations of the one or more data structures in the DNN. The hybrid memory includes at least a first memory and a second memory that differ according to write endurance attributes.

公开(公告)号：US20210296234A1

公开(公告)日：2021-09-23

申请号：US16822803

申请日：2020-03-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel James Dechene ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Somnath Ghosh ,  Carl Radens

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Power distribution fabrics and methods of forming the same include forming a first layer of parallel conductive lines, having a first width. At least one additional layer of conductive lines is formed over the first layer of conductive lines, with the conductive lines of each successive layer in the at least one additional layer having a different orientation and a different width relative to the conductive lines of the preceding layer.

公开(公告)号：US11038106B1

公开(公告)日：2021-06-15

申请号：US16691646

申请日：2019-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Carl Radens ,  Kangguo Cheng ,  Juntao Li ,  Ruilong Xie

IPC: H01L45/00

Abstract: A method may include filling a via opening with a spacer, the via opening formed in a dielectric layer, forming a trench within the spacer, filling the trench with a metal layer, recessing the spacer to form an opening and expose an upper portion of the metal layer, wherein the exposed portion of the metal layer is formed into a cone shaped tip, conformally depositing a liner along a bottom and a sidewall of the opening and the exposed portion of the metal layer, depositing a second dielectric layer along the bottom of the opening on top of the liner, recessing the liner to form a channel and partially exposing a sidewall of the second dielectric layer and a sidewall of the metal layer, depositing a third dielectric layer in the channel, and depositing a phase change memory layer within the opening.

公开(公告)号：US20200058801A1

公开(公告)日：2020-02-20

申请号：US16591873

申请日：2019-10-03

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Lawrence A. Clevenger ,  Carl Radens ,  Junli Wang ,  John H. Zhang

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/088 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417

Abstract: A technique relates to a semiconductor device. A first stack includes a first plurality of nanowires respectively coupled to first source and drain regions, and a second stack includes a second plurality of nanowires respectively coupled to second source and drain regions. First source and drain contacts couple to a first predefined number of the first plurality of nanowires. Second source and drain contacts to couple to a second predefined number of the second plurality of nanowires, wherein the first predefined number is different from the second predefined number.

公开(公告)号：US10546743B2

公开(公告)日：2020-01-28

申请号：US15874654

申请日：2018-01-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Yann Mignot ,  Lawrence A. Clevenger ,  Carl Radens ,  Richard Stephen Wise ,  Yiheng Xu ,  Yannick Loquet ,  Hsueh-Chung Chen

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

公开(公告)号：US10325777B2

公开(公告)日：2019-06-18

申请号：US15690540

申请日：2017-08-30

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  John H. Zhang ,  Carl Radens

IPC: H01L21/302 ,  H01L21/308 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

Abstract: A chemical material is deposited on a surface of a substrate. A mandrel composition is deposited on a surface of the chemical material. A mandrel hard mask pattern is deposited on a surface of the mandrel composition. The mandrel composition is etched. The mandrel hard mask pattern is removed. A plurality of spacer materials are deposited sequentially onto a surface of the chemical material and a surface of the mandrel composition. A portion of each of the plurality of spacer materials are removed sequentially. A remainder of the mandrel composition is removed. The substrate is etched. The chemical material and at least one of the spacer materials of the plurality of spacer materials are removed.

公开(公告)号：US20190067024A1

公开(公告)日：2019-02-28

申请号：US15801039

申请日：2017-11-01

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  John H. Zhang ,  Carl Radens

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: A chemical material is deposited on a surface of a substrate. A mandrel composition is deposited on a surface of the chemical material. A mandrel hard mask pattern is deposited on a surface of the mandrel composition. The mandrel composition is etched. The mandrel hard mask pattern is removed. A plurality of spacer materials are deposited sequentially onto a surface of the chemical material and a surface of the mandrel composition. A portion of each of the plurality of spacer materials are removed sequentially. A remainder of the mandrel composition is removed. The substrate is etched. The chemical material and at least one of the spacer materials of the plurality of spacer materials are removed.

公开(公告)号：US09659818B1

公开(公告)日：2017-05-23

申请号：US15336859

申请日：2016-10-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Carl Radens ,  John Zhang

IPC: H01L21/311 ,  H01L21/768 ,  H01L29/66 ,  H01L21/033

CPC classification number: H01L21/76883 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/6656

Abstract: A method for forming conductive lines on a substrate includes depositing a layer of mandrel material on a substrate and removing portions of the layer of mandrel material to form a first mandrel having a first length, a portion of the first mandrel has sloped sidewalls, a second mandrel having a second length, the second mandrel having an outwardly facing sloped sidewall, and a third mandrel having the second length, the third mandrel having an outwardly facing sloped sidewall, the first length is greater than the second length, the first mandrel is arranged between the second mandrel and the third mandrel. A spacer is formed along non-sloped sidewalls of the first mandrel, the second mandrel, and the third mandrel. The first mandrel, the second mandrel, and the third, mandrel, and exposed portions of the substrate are removed to form cavities. The cavities are filled with a conductive material.

公开(公告)号：US09646939B2

公开(公告)日：2017-05-09

申请号：US15090996

申请日：2016-04-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Byoung Youp Kim ,  Walter Kleemeier

IPC: H01L21/4763 ,  H01L23/00 ,  H01L21/768 ,  H01L21/66 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76897 ,  H01L22/12 ,  H01L22/14 ,  H01L22/32 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.