-
公开(公告)号：US08234439B2
公开(公告)日：2012-07-31
申请号：US13154150
申请日：2011-06-06
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： G06F12/00
CPC分类号： G06F12/0223 , G06F11/1068 , G06F12/0246 , G06F2212/2022 , G06F2212/7208 , G11C29/765
摘要： Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices.
摘要翻译： 公开了诸如将数据存储在具有卷积编码的诸如NAND闪存的多个非易失性集成电路存储器件中的装置和方法。 卷积码的相对较高的码率消耗相对较小的额外的存储空间。 在一个实施例中，卷积码扩展到多个存储器件的部分上，而不是集中在特定存储器件的页面内。 在一个实施例中，使用m / n的码率，并且卷积码被存储在n个存储器装置中。
-
公开(公告)号：US20120144263A1
公开(公告)日：2012-06-07
申请号：US13371683
申请日：2012-02-13
CPC分类号： G06F11/10 , G06F11/1048 , H03M13/132 , H03M13/1515
摘要： Methods include receiving data and an ECC code read from a memory array, generating an ECC code from the received data, and determining whether the received data is corrupted by evaluating the generated ECC code against the ECC code read from the memory array. If the received data is determined to be corrupted, a correction algorithm and a recorded likely state of a known bad/questionable bit of the received data may be used to correct error in the received data. Alternatively, if the received data is determined to be corrupted, the correction algorithm and a recorded location of a known bad/questionable bit of the received data may be used to correct error in the received data.
摘要翻译： 方法包括从存储器阵列接收数据和从其读取的ECC代码，从接收到的数据生成ECC代码，并且通过根据从存储器阵列读取的ECC代码评估所生成的ECC代码来确定接收的数据是否被破坏。 如果接收到的数据被确定为被破坏，则可以使用接收到的数据的已知的坏/可疑比特的校正算法和记录的可能状态来校正接收到的数据中的错误。 或者，如果接收到的数据被确定为已被破坏，则可以使用校正算法和接收到的数据的已知坏/可疑位的记录位置来校正接收到的数据中的错误。
-
公开(公告)号：US08125826B2
公开(公告)日：2012-02-28
申请号：US12949347
申请日：2010-11-18
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G06F11/1008 , G11C11/5621 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C16/10 , G11C29/00 , G11C2211/5641
摘要： Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2B, rounded up to an integer, and where B is equal to the fractional number of bits represented by the programmed state.
摘要翻译： 用于编程存储器单元的方法，设备，模块和系统可以包括存储与在一组存储器单元中表示整数位的数据状态相对应的电荷。 编程存储器单元可以包括将电荷存储在组的单元中，其中电荷对应于编程状态，其中编程状态表示分数位数，并且其中编程状态表示数据状态的数字，如 基数N中的数，其中N等于2B，向上舍入为整数，并且其中B等于由编程状态表示的分数的位数。
-
公开(公告)号：US20110258425A1
公开(公告)日：2011-10-20
申请号：US12762049
申请日：2010-04-16
IPC分类号： G06F15/177 , G06F12/02
CPC分类号： G06F9/5077 , G06F3/062 , G06F3/0644 , G06F3/0679 , G06F9/4401 , G06F12/0246 , G06F2212/7206
摘要： The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.
摘要翻译： 本公开包括存储器设备和系统中的引导分区以及与其相关联的方法。 一个或多个实施例包括存储器单元的阵列，其中阵列包括引导分区和多个附加分区。 顺序逻辑单元标识符与附加分区相关联，并且与顺序逻辑单元标识符不一致的逻辑单元标识符与引导分区相关联。
-
公开(公告)号：US08023334B2
公开(公告)日：2011-09-20
申请号：US12262405
申请日：2008-10-31
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C5/063 , G11C11/5628 , G11C11/5642 , G11C16/10
摘要： A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal line propagation delay, such as determining an amount of error due to the delay, and pre-compensating the programmed threshold voltage of the memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Alternatively, memory cell signal line propagation delay can be post-compensated for, or the pre-compensation fine tuned, after sensing the threshold voltages of the selected memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Other methods, devices, etc., are also disclosed.
摘要翻译： 描述了补偿存储器单元信号线传播延迟的存储器件和编程和/或读取过程，例如增加总体阈值电压范围和可用的非易失性存储器单元状态。 可以通过表征存储单元信号线传播延迟来实现存储单元信号线传播延迟补偿，例如确定由于延迟引起的误差量，并且基于误差量预先补偿存储器单元的编程阈值电压 由所选存储单元信号线上的存储单元信号线传播延迟和单元位置引起。 或者，可以基于由存储器单元信号线传播延迟和单元引起的误差量感测所选择的存储器单元的阈值电压之后，对存储单元信号线传播延迟进行后补偿或预补偿微调 所选存储单元信号线上的位置。 还公开了其他方法，装置等。
-
公开(公告)号：US07900162B2
公开(公告)日：2011-03-01
申请号：US12394282
申请日：2009-02-27
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： H03K17/693
CPC分类号： G11C7/1051 , G11C7/1063 , G11C16/26
摘要： A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed back to the controller circuit that then uses the fed back signal to read the data from the data/IO bus.
摘要翻译： 控制器电路通过数据/ IO总线和控制总线耦合到存储器件。 控制器电路产生读取使能信号，该信号被发送到存储器件以指示存储器件将数据驱动到数据/ IO总线上。 读使能信号反馈到控制器电路，然后使用反馈信号从数据/ IO总线读取数据。
-
公开(公告)号：US20110022932A1
公开(公告)日：2011-01-27
申请号：US12897260
申请日：2010-10-04
申请人： William H. Radke
发明人： William H. Radke
CPC分类号： H03M13/05 , G06F11/1068
摘要： Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by increasing the data area of user data being covered by the ECC code. This averages any possible bit errors over a larger data area and allows a greater number of errors to be corrected by a combining the ECC codes in the coverage area without substantially changing the overall size of ECC codes being stored over a single sector approach. In one embodiment of the present invention, the size of the data block utilized for ECC coverage is variable and can be selected such that differing areas of the memory array or data types can have a differing ECC data coverage sizes. It is also noted that the ECC algorithm, math base or encoding scheme can also be varied between these differing areas of the memory array.
摘要翻译： 描述了改进的存储器件，电路和数据方法，其通过增加由ECC代码覆盖的用户数据的数据区域来促进对存储器系统或器件中的数据的检测和校正。 这样可以在更大的数据区域上平均任何可能的位错误，并且允许通过组合覆盖区域中的ECC码来校正更多数量的错误，而不会基本上改变通过单个扇区方法存储的ECC码的总体大小。 在本发明的一个实施例中，用于ECC覆盖的数据块的大小是可变的，并且可以选择使得存储器阵列或数据类型的不同区域可以具有不同的ECC数据覆盖尺寸。 还应注意的是，ECC算法，数学基础或编码方案也可以在存储器阵列的这些不同区域之间变化。
-
公开(公告)号：US07739576B2
公开(公告)日：2010-06-15
申请号：US11513571
申请日：2006-08-31
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： H03M13/00
CPC分类号： G06F11/10 , B32B25/08 , B32B27/08 , F16L2011/047 , G06F11/1068 , G11C2029/0411
摘要： Memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory controllers, memory systems, and/or non-volatile memory devices by allowing the number of ECC check bytes being utilized to be varied to increase or decrease the ECC check depth. This allows the depth of the ECC coverage (the overall number of bit errors detectable and/or correctable in each sector by the stored ECC check bytes) to be selected based on the application, the amount of available data storage for ECC check bytes in the overhead/spare area associated with the sector, the version of memory device or controller being utilized, or the number of errors being seen in the memory system, device, bank, erase block, or sector (the error incidence rate), while the base data size of the area (sector) covered by the ECC check bytes stays the same.
摘要翻译： 描述的存储器件，电路和数据方法通过允许ECC校验字节的数量被改变来增加或减少，从而便于检测和校正存储器控制器，存储器系统和/或非易失性存储器件中的数据 ECC检查深度。 这允许基于应用来选择ECC覆盖的深度（通过存储的ECC检查字节在每个扇区中可检测和/或可校正的位错误的总数），用于ECC中的ECC校验字节的可用数据存储量 与扇区相关联的开销/备用区域，正在使用的存储设备或控制器的版本，或存储器系统，设备，存储体，擦除块或扇区中的错误数量（错误发生率），而基础 由ECC检查字节覆盖的区域（扇区）的数据大小保持不变。
-
公开(公告)号：US20100124133A1
公开(公告)日：2010-05-20
申请号：US12274426
申请日：2008-11-20
申请人： Vishal Sarin , Dzung H. Nguyen , William H. Radke
发明人： Vishal Sarin , Dzung H. Nguyen , William H. Radke
CPC分类号： G11C29/04 , G11C29/808 , G11C29/82 , G11C29/848
摘要： Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective memory block of a sequence of memory blocks of the memory device in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block.
摘要翻译： 提供了操作存储器件的电子系统和方法。 在一个这样的实施例中，存储器设备接收外部地址，其代替存储器块序列的缺陷存储器块来寻址存储器件的一系列存储器块的无缺陷存储器块，使得无缺陷存储器 块代替有缺陷的内存块。 在缺陷存储器块之后的无缺陷存储器块是可用于替换有缺陷的存储器块的存储器块序列中的缺陷存储器块之后的非缺陷存储块。
-
公开(公告)号：US20100110798A1
公开(公告)日：2010-05-06
申请号：US12262405
申请日：2008-10-31
IPC分类号： G11C16/10
CPC分类号： G11C16/26 , G11C5/063 , G11C11/5628 , G11C11/5642 , G11C16/10
摘要： A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal line propagation delay, such as determining an amount of error due to the delay, and pre-compensating the programmed threshold voltage of the memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Alternatively, memory cell signal line propagation delay can be post-compensated for, or the pre-compensation fine tuned, after sensing the threshold voltages of the selected memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Other methods, devices, etc., are also disclosed.
摘要翻译： 描述了补偿存储器单元信号线传播延迟的存储器件和编程和/或读取过程，例如增加总体阈值电压范围和可用的非易失性存储器单元状态。 可以通过表征存储单元信号线传播延迟来实现存储单元信号线传播延迟补偿，例如确定由于延迟引起的误差量，并且基于误差量预先补偿存储器单元的编程阈值电压 由所选存储单元信号线上的存储单元信号线传播延迟和单元位置引起。 或者，可以基于由存储器单元信号线传播延迟和单元引起的误差量感测所选择的存储器单元的阈值电压之后，对存储单元信号线传播延迟进行后补偿或预补偿微调 所选存储单元信号线上的位置。 还公开了其他方法，装置等。
-
-
-
-
-
-
-
-
-
搜索结果
124 条记录 (耗时 0.04 秒)
