公开(公告)号：US20070166890A1

公开(公告)日：2007-07-19

申请号：US11335763

申请日：2006-01-19

申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

IPC分类号： H01L21/84

CPC分类号： H01L29/66742 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78687

摘要： In a first aspect, a first method of manufacturing a PFET on a substrate is provided. The first method includes the steps of (1) forming a gate channel region of the PFET having a first thickness on the substrate; and (2) forming at least one composite source/drain diffusion region of the PFET having a second thickness greater than the first thickness on the substrate. The at least one composite source/drain diffusion region is adapted to cause a strain in the gate channel region. Further, significantly all of the at least one composite source/drain diffusion region is below a bottom surface of a gate of the PFET. Numerous other aspects are provided.

摘要翻译： 在第一方面中，提供了在衬底上制造PFET的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成具有第一厚度的PFET的栅极沟道区; 和（2）在衬底上形成具有大于第一厚度的第二厚度的PFET的至少一个复合源极/漏极扩散区域。 至少一个复合源极/漏极扩散区域适于在栅极沟道区域引起应变。 此外，显着地所有的至少一个复合源极/漏极扩散区域在PFET的栅极的底表面之下。 提供了许多其他方面。

公开(公告)号：US20070096797A1

公开(公告)日：2007-05-03

申请号：US11163688

申请日：2005-10-27

申请人： Hibourahima Camara ,  Louis Hsu ,  James Rockrohr ,  Karl Selander ,  Huihao Xu ,  Steven Zier

发明人： Hibourahima Camara ,  Louis Hsu ,  James Rockrohr ,  Karl Selander ,  Huihao Xu ,  Steven Zier

IPC分类号： G05F1/10

CPC分类号： H03K17/223 ,  G05F3/262 ,  G11C5/144 ,  G11C5/145 ,  G11C7/20 ,  H03K17/08

摘要： A system for protecting a weak device operating in micro-electronic circuit that includes a high voltage power supply from high voltage overstressing prevents the weak device from failing during power-up, power-down, and when a low voltage power supply in a multiple power supply system is absent. The system includes a low voltage power supply detection circuit configured to detect circuit power-up, circuit power-down, and when the low voltage power supply is absent, and generate a control signal upon detection. The system further includes a controlled current mirror device configured to provide a trickle current to maintain a conduction channel in the weak device in response to the control signal received from the low voltage power supply detection circuit during circuit power-up, circuit power-down, and when the low voltage power supply is absent.

摘要翻译： 用于保护微电子电路中操作的弱电装置的系统包括来自高压过应力的高电压电源，防止在上电，掉电期间以及当多功率电源中的低电压电源时弱装置发生故障 供应系统不存在。 该系统包括低电压电源检测电路，其被配置为检测电路上电，电路掉电以及当低电压电源不存在时，并且在检测时产生控制信号。 该系统还包括被配置为提供涓流电流的受控电流镜装置，以响应于在电路加电，电路断电期间从低电压电源检测电路接收的控制信号来保持弱装置中的导通通道， 并且当低电压电源不存在时。

公开(公告)号：US20070096319A1

公开(公告)日：2007-05-03

申请号：US11266741

申请日：2005-11-03

申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5329 ,  H01L21/7682 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.

摘要翻译： 一种用于制造和后端（BEOL）金属化结构的方法包括同时存在的高k和低k电介质区域。 互连结构包括第一层间电介质（ILD）层和具有位于第二ILD层下面的第一ILD层的第二ILD层。 在第一ILD中形成多个柱状气隙。 使用两相光致抗蚀剂材料制造柱状气隙结构，用于在随后的处理期间提供不同的蚀刻选择性。

公开(公告)号：US20070054489A1

公开(公告)日：2007-03-08

申请号：US11503259

申请日：2006-08-14

申请人： Kwong Wong ,  Louis Hsu ,  Timothy Dalton ,  Carl Radens ,  Chih-Chao Yang ,  Lawrence Clevenger ,  Theodorus Standaert

发明人： Kwong Wong ,  Louis Hsu ,  Timothy Dalton ,  Carl Radens ,  Chih-Chao Yang ,  Lawrence Clevenger ,  Theodorus Standaert

IPC分类号： H01L21/44

CPC分类号： H01L21/76852 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an interconnect that includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.

摘要翻译： 一种制造互连的方法，包括在电介质材料中提供互连结构，使电介质材料凹陷，使得互连结构的一部分在电介质的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。

公开(公告)号：US20070045749A1

公开(公告)日：2007-03-01

申请号：US11551959

申请日：2006-10-23

申请人： Wilfried Haensch ,  Terence Hook ,  Louis Hsu ,  Rajiv Joshi ,  Werner Rausch

发明人： Wilfried Haensch ,  Terence Hook ,  Louis Hsu ,  Rajiv Joshi ,  Werner Rausch

IPC分类号： H01L29/76

CPC分类号： H01L29/78 ,  H01L21/823892 ,  H01L27/0928

摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

摘要翻译： 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

公开(公告)号：US20070045697A1

公开(公告)日：2007-03-01

申请号：US11216386

申请日：2005-08-31

申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

IPC分类号： H01L27/108

CPC分类号： H01L21/84 ,  H01L27/0218 ,  H01L27/10841 ,  H01L27/1203 ,  H01L29/66545

摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.

摘要翻译： 一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括建立在绝缘体上半导体（SOI）晶片上的多个垂直存储单元和SOI晶片的埋入介质层中的体接触。 体接触将半导体本体与一个垂直存储单元的存取器件的沟道区和SOI晶片的半导体衬底电耦合。 身体接触提供了一种电流泄漏路径，可减少浮体对垂直记忆体的影响。 体接触可以通过离子注入工艺形成，该方法改变掩埋介电层的区域的化学计量，使得改性区域以相对较高的电阻变为导电性。

公开(公告)号：US20070007601A1

公开(公告)日：2007-01-11

申请号：US11509866

申请日：2006-08-25

申请人： Louis Hsu ,  Oleg Gluschenkov ,  Jack Mandelman ,  Carl Radens

发明人： Louis Hsu ,  Oleg Gluschenkov ,  Jack Mandelman ,  Carl Radens

IPC分类号： H01L21/8244 ,  H01L29/94 ,  H01L29/76

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.

摘要翻译： 形成SRAM单元装置的方法包括以下步骤。 形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为形成在平面绝缘体上的平行岛的硅层。 通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到 到共同的身体层。 形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。 然后，连接FET晶体管以形成SRAM单元。

公开(公告)号：US20060286781A1

公开(公告)日：2006-12-21

申请号：US11154907

申请日：2005-06-16

申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti

发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L21/00 ,  H01L21/20

CPC分类号： H01L29/045 ,  H01L21/84 ,  H01L27/1203

摘要： Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the apertures in the patterned insulating layer with amorphous silicon to define a plurality of amorphous silicon features, and re-growing the amorphous silicon features to define a thin active silicon layer consisting of regrown silicon features. The amorphous silicon features may be regrown such that a number have a first crystal orientation and another number have a different second crystal orientation.

摘要翻译： 通过晶体压印或镶嵌法在绝缘基板上形成由活性硅层薄的特征的半导体结构的方法。 所述方法包括图案化绝缘层以限定多个孔，用非晶硅填充图案化绝缘层中的孔以限定多个非晶硅特征，以及重新生长非晶硅特征以限定薄的有源硅层， 的再生硅特征。 可以重新生长非晶硅特征，使得数量具有第一晶体取向，而另一数目具有不同的第二晶体取向。

公开(公告)号：US20060274681A1

公开(公告)日：2006-12-07

申请号：US10908959

申请日：2005-06-02

申请人： Louis Hsu ,  Karl Selander ,  Michael Sorna ,  Daniel Storaska

发明人： Louis Hsu ,  Karl Selander ,  Michael Sorna ,  Daniel Storaska

IPC分类号： H04B1/58

CPC分类号： G06F13/4072

摘要： An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling element includes an isolating circuit coupled to the first conductor, a second conductor operable to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. The signal-handling circuit is operable to perform a signal-handling function in response to the output of the isolating circuit. By virtue of the isolating circuit, the signal-handling circuit and the first circuit are isolated from the second conductor and the signal-handling circuit. Preferably, the achieved isolation permits a communication signal included in the first signal to be conducted within a communication apparatus with less capacitance, and producing less return loss of that signal.

摘要翻译： 提供一种装置，其包括可操作以传导第一信号的公共信号节点，耦合到公共信号节点以利用第一信号的第一电路和耦合到公共信号节点的信号处理元件。 信号处理元件包括耦合到第一导体的隔离电路，可操作以导通隔离电路的输出的第二导体和耦合到第二导体的信号处理电路。 信号处理电路可操作以响应于隔离电路的输出执行信号处理功能。 通过隔离电路，信号处理电路和第一电路与第二导体和信号处理电路隔离。 优选地，所实现的隔离允许包含在第一信号中的通信信号在具有较小电容的通信设备内传导，并且产生较小的该信号的回波损耗。

公开(公告)号：US20060189110A1

公开(公告)日：2006-08-24

申请号：US11064730

申请日：2005-02-24

申请人： Jack Mandelman ,  Louis Hsu ,  Rajiv Joshi

发明人： Jack Mandelman ,  Louis Hsu ,  Rajiv Joshi

IPC分类号： H01L21/3205

CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1203 ,  H01L29/94

摘要： A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

摘要翻译： 提供一种具有体电容板的半导体结构，其形成有确保体电容板与源极线（SL）扩散和位线扩散两者自对准的工艺。 因此，SL和位线扩散和体电容板之间的重叠量被精确地控制。 更具体地说，本发明通过使用确保存在1）板和源极/漏极扩散之间的最小重叠的过程形成具有侧壁电容器板的1T无电容的SOI体电荷存储单元的结构，以及2）最小重叠 在本发明中获得的精确控制并且不受对准公差的影响。 与现有技术相比，本发明的电池产生更大的信号余量，改善的性能，更小的芯片尺寸和降低的动态功耗。