公开(公告)号：US07888224B2

公开(公告)日：2011-02-15

申请号：US12271262

申请日：2008-11-14

申请人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

发明人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

摘要翻译： 一种在晶体半导体衬底中形成浅结区的方法和用于制造具有浅结区的半导体器件的方法包括：缺陷工程步骤，其中将第一离子引入衬底的第一区域，并且在第一衬底中产生空位 地区。 在产生衬底空位期间，第一区域保持基本上结晶。 在第二区域中产生间质物质，并且将第二离子引入第二区域以捕获间质物质。 激光退火用于激活第一区域中的掺杂物质并修复第二区域中的植入损伤。 缺陷工程过程产生空位丰富的表面区域，其中在MOS器件中产生具有高掺杂剂激活和低薄层电阻的源极和漏极延伸区域。

公开(公告)号：US07573081B2

公开(公告)日：2009-08-11

申请号：US11519103

申请日：2006-09-11

申请人： Lap Chan ,  Kok Wai Johnny Chew ,  Cher Liang Cha ,  Chee Tee Chua

发明人： Lap Chan ,  Kok Wai Johnny Chew ,  Cher Liang Cha ,  Chee Tee Chua

IPC分类号： H01L29/78

CPC分类号： H01L21/76834 ,  H01F3/14 ,  H01F17/0006 ,  H01F27/34 ,  H01F41/041 ,  H01F41/045 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/5227 ,  H01L23/53295 ,  H01L27/08 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

摘要翻译： 提供了一种在硅衬底的表面上形成电感器的新方法。 本发明提供金属电感器下面的氧化物鳍片的覆盖层。 氧化物鳍片为上覆的金属电感器提供了稳定的支持，同时也允许水平空气柱同时存在于电感器下面。 通过重复施用所使用的掩模，可以在本发明的基础上产生空间上插入在所产生的氧化物翅片的覆盖层之间的空腔的覆盖层。 衬底表面上的空穴的存在显着降低了与衬底相关联的电感器的寄生电容和串联电阻。

公开(公告)号：US20080284552A1

公开(公告)日：2008-11-20

申请号：US11750341

申请日：2007-05-18

申请人： Chee Chong Lim ,  Kok Wai Chew ,  Kiat Seng Yeo ,  Suh Fei Lim ,  Manh Anh Do ,  Lap Chan

发明人： Chee Chong Lim ,  Kok Wai Chew ,  Kiat Seng Yeo ,  Suh Fei Lim ,  Manh Anh Do ,  Lap Chan

IPC分类号： H01F5/00

CPC分类号： H01F17/0006 ,  H01F17/0013 ,  H01F19/08 ,  H01F27/2804 ,  H01F41/041 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/4902 ,  H01L2924/00

摘要： An integrated transformer structure includes a first coil element associated with a transverse axis, the first coil element having at least one turn. The first coil element includes a first portion provided on a first lateral level, and a second portion provided on a second lateral level. The first and second lateral levels being mutually spaced apart along said transverse axis. The first and second portions being displaced laterally from said axis by different respective distances. At least one crossover portion of the first coil element, in which the first coil element being configured to provide a conducting path through at least a portion of the first portion of the first coil element to the crossover portion, through the crossover portion and subsequently through at least a portion of the second portion of the first coil element, in which any change of flow direction along said path is less than 90° in a lateral direction.

摘要翻译： 集成变压器结构包括与横向轴线相关联的第一线圈元件，第一线圈元件具有至少一匝。 第一线圈元件包括设置在第一横向水平面上的第一部分和设置在第二横向水平面上的第二部分。 第一和第二横向水平面沿着所述横向轴线相互间隔开。 第一和第二部分从所述轴线横向移位不同的相应距离。 所述第一线圈元件的至少一个交叉部分，其中所述第一线圈元件被配置为提供通过所述交叉部分穿过所述交叉部分的所述第一线圈元件的所述第一部分的至少一部分的导电路径，并且随后通过 第一线圈元件的第二部分的至少一部分，其中沿着所述路径的流动方向的任何变化在横向方向上小于90°。

公开(公告)号：US07105420B1

公开(公告)日：2006-09-12

申请号：US09413177

申请日：1999-10-07

申请人： Lap Chan ,  Kok Wai Johnny Chew ,  Cher Liang Cha ,  Chee Tee Chua

发明人： Lap Chan ,  Kok Wai Johnny Chew ,  Cher Liang Cha ,  Chee Tee Chua

IPC分类号： H01L21/76

CPC分类号： H01L21/76834 ,  H01F3/14 ,  H01F17/0006 ,  H01F27/34 ,  H01F41/041 ,  H01F41/045 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/5227 ,  H01L23/53295 ,  H01L27/08 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

公开(公告)号：US07049201B2

公开(公告)日：2006-05-23

申请号：US10703297

申请日：2003-11-06

申请人： Purakh Raj Verma ,  Shao-Fu Sanford Chu ,  Lap Chan ,  Jian Xun Li ,  Jia Zhen Zheng

发明人： Purakh Raj Verma ,  Shao-Fu Sanford Chu ,  Lap Chan ,  Jian Xun Li ,  Jia Zhen Zheng

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.

摘要翻译： 一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，半导体衬底上的多个绝缘层的半导体衬底，在集电极区域上具有基腔的多个绝缘层中的至少一个， 基腔中的复合半导体材料的基底结构，在基底腔上的绝缘层中的窗口，窗口中的发射极结构，层间介电层以及通过层间介电层到基底结构的连接，发射极 结构和收集器区域。 基底结构和发射极结构优选地形成在相同的处理室中。

公开(公告)号：US07030451B2

公开(公告)日：2006-04-18

申请号：US11081908

申请日：2005-03-15

申请人： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

发明人： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

IPC分类号： H01L29/78

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

公开(公告)号：US06924202B2

公开(公告)日：2005-08-02

申请号：US10683142

申请日：2003-10-09

申请人： Jian Xun Li ,  Lap Chan ,  Purakh Raj Verma ,  Jia Zhen Zheng ,  Shao-fu Sanford Chu

发明人： Jian Xun Li ,  Lap Chan ,  Purakh Raj Verma ,  Jia Zhen Zheng ,  Shao-fu Sanford Chu

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/7378

摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector region. An intrinsic base structure having a sidewall portion and a bottom portion is formed in the base trench. An insulating spacer is formed over the sidewall portion of the intrinsic base structure, and an emitter structure is formed over the insulating spacer and the bottom portion of the intrinsic base structure. An interlevel dielectric layer is formed over the base contact layer and the emitter structure. Connections are formed through the interlevel dielectric layer to the collector region, the base contact layer, and the emitter structure. The intrinsic base structure is silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

摘要翻译： 提供了具有集电极区域的半导体衬底的异质结双极晶体管（HBT）及其制造方法。 基极接触层形成在集电极区域上，基底沟槽形成在基极接触层和集电极区域中。 在基底沟槽中形成具有侧壁部分和底部的本征基底结构。 在本征基底结构的侧壁部分上形成绝缘间隔物，并且在绝缘间隔物和本征基底结构的底部上形成发射极结构。 在基极接触层和发射极结构之上形成层间电介质层。 通过层间绝缘层到集电极区，基极接触层和发射极结构形成连接。 本征基础结构是硅和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

公开(公告)号：US06908824B2

公开(公告)日：2005-06-21

申请号：US10703284

申请日：2003-11-06

申请人： Jian Xun Li ,  Lap Chan ,  Purakh Raj Verma ,  Jia Zhen Zheng ,  Shao-fu Sanford Chu

发明人： Jian Xun Li ,  Lap Chan ,  Purakh Raj Verma ,  Jia Zhen Zheng ,  Shao-fu Sanford Chu

IPC分类号： H01L21/331 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

摘要翻译： 提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。 基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。 半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。 基底结构形成在基底沟槽中。 通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。 基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

公开(公告)号：US06881976B1

公开(公告)日：2005-04-19

申请号：US10705163

申请日：2003-11-06

申请人： Jia Zhen Zheng ,  Lap Chan ,  Shao-fu Sanford Chu

发明人： Jia Zhen Zheng ,  Lap Chan ,  Shao-fu Sanford Chu

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/108 ,  H01L29/04 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L27/0623

摘要： A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.

摘要翻译： 因此，提供BiCMOS半导体及其制造方法。 提供具有集电极区域的半导体衬底。 在集电极区域上形成伪栅极。 在伪栅极中形成发射器窗口以形成外部基极结构。 在伪栅极的一部分下面的底切区域形成为在底切区域中提供内部基极结构。 发射极结构在内部基极结构的发射极窗口中形成。 在半导体衬底上形成层间电介质层，并且通过层间电介质层到集电极区域，非本征基极结构和发射极结构形成连接。 本征基础结构包括诸如硅和硅 - 锗的复合半导体材料或硅 - 锗 - 碳或其组合。

公开(公告)号：US20050079658A1

公开(公告)日：2005-04-14

申请号：US10683142

申请日：2003-10-09

申请人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-Fu Chu

发明人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-Fu Chu

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/7378

摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector region. An intrinsic base structure having a sidewall portion and a bottom portion is formed in the base trench. An insulating spacer is formed over the sidewall portion of the intrinsic base structure, and an emitter structure is formed over the insulating spacer and the bottom portion of the intrinsic base structure. An interlevel dielectric layer is formed over the base contact layer and the emitter structure. Connections are formed through the interlevel dielectric layer to the collector region, the base contact layer, and the emitter structure. The intrinsic base structure is silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.