公开(公告)号：US11610917B2

公开(公告)日：2023-03-21

申请号：US17568652

申请日：2022-01-04

申请人： Intel Corporation

发明人： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC分类号： H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US11562999B2

公开(公告)日：2023-01-24

申请号：US16147733

申请日：2018-09-29

申请人： Intel Corporation

发明人： Roman Olac-Vaw ,  Nick Lindert ,  Chia-Hong Jan ,  Walid Hafez

IPC分类号： H01L27/06 ,  H01L27/07 ,  H01L49/02 ,  H01L29/51 ,  H01L29/78 ,  H01L21/027 ,  H01L29/66 ,  H01L23/522 ,  H01L23/00

摘要： A method for fabricating a semiconductor structure includes forming a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is formed over a first of the plurality of semiconductor fins. A second gate structure is formed over a second of the plurality of semiconductor fins. A gate edge isolation structure is formed laterally between and in contact with the first gate structure and the second gate structure, the gate edge isolation structure on the trench isolation region and extending above an uppermost surface of the first gate structure and the second gate structure. A precision resistor is formed on the gate edge isolation structure, wherein the precision resistor and the first gate structure and second gate structure comprise a same material layer.

公开(公告)号：US20220157729A1

公开(公告)日：2022-05-19

申请号：US17649637

申请日：2022-02-01

申请人： Intel Corporation

发明人： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC分类号： H01L23/538 ,  H01L21/768

摘要： An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

公开(公告)号：US11329138B2

公开(公告)日：2022-05-10

申请号：US15943552

申请日：2018-04-02

申请人： Intel Corporation

发明人： Sairam Subramanian ,  Christopher Kenyon ,  Sridhar Govindaraju ,  Chia-Hong Jan ,  Mark Liu ,  Szuya S. Liao ,  Walid M. Hafez

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

摘要： Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.

公开(公告)号：US10930729B2

公开(公告)日：2021-02-23

申请号：US16328704

申请日：2016-10-21

申请人： Intel Corporation

发明人： Chia-Hong Jan ,  Walid M. Hafez ,  Neville L. Dias ,  Rahul Ramaswamy ,  Hsu-Yu Chang ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC分类号： H01L49/02 ,  H01L21/285 ,  H01L21/306 ,  H01L27/06 ,  C23C16/455

摘要： Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.

公开(公告)号：US10923574B2

公开(公告)日：2021-02-16

申请号：US16569879

申请日：2019-09-13

申请人： INTEL CORPORATION

发明人： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Jui-Yen Lin ,  Chia-Hong Jan

IPC分类号： H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/3213 ,  H01L21/764 ,  H01L29/78 ,  H01L29/51 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08

摘要： Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US10854757B2

公开(公告)日：2020-12-01

申请号：US16344226

申请日：2016-12-13

申请人： Intel Corporation

发明人： Rahul Ramaswamy ,  Hsu-Yu Chang ,  Chia-Hong Jan ,  Walid M. Hafez ,  Neville L. Dias ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423

摘要： A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.

公开(公告)号：US10761264B2

公开(公告)日：2020-09-01

申请号：US16462077

申请日：2016-12-30

申请人： Intel Corporation

发明人： Rahul Ramaswamy ,  Chia-Hong Jan ,  Walid Hafez ,  Neville Dias ,  Hsu-Yu Chang ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC分类号： G02B6/122 ,  G02B6/12 ,  G02B6/00 ,  H01P3/16 ,  G02B6/134 ,  G02B6/136

摘要： Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.

公开(公告)号：US10756210B2

公开(公告)日：2020-08-25

申请号：US16317708

申请日：2016-09-30

申请人： Intel Corporation

发明人： Chia-Hong Jan ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Neville L. Dias ,  Rahul Ramaswamy ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC分类号： H01L51/05 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786

摘要： A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.

公开(公告)号：US10204999B2

公开(公告)日：2019-02-12

申请号：US15743847

申请日：2015-07-17

申请人： Intel Corporation

发明人： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC分类号： H01L29/49 ,  H01L21/764 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

摘要： A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.