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    Methods of forming memory cells
    112.
    发明授权
    Methods of forming memory cells 有权

    公开(公告)号：US10153433B2

    公开(公告)日：2018-12-11

    申请号：US15670986

    申请日：2017-08-07

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Giorgio Servalli ,  Carmela Cupeta ,  Fabio Pellizzer

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

    Constructions comprising stacked memory arrays
    113.
    发明授权
    Constructions comprising stacked memory arrays 有权

    公开(公告)号：US10147764B2

    公开(公告)日：2018-12-04

    申请号：US15845938

    申请日：2017-12-18

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.

    Three dimensional memory array
    114.
    发明授权
    Three dimensional memory array 有权

    公开(公告)号：US10096655B1

    公开(公告)日：2018-10-09

    申请号：US15482016

    申请日：2017-04-07

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli

    IPC: H01L29/06 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.

    METHODS OF FORMING PHASE CHANGE MEMORY APPARATUSES
    120.
    发明申请
    METHODS OF FORMING PHASE CHANGE MEMORY APPARATUSES 审中-公开

    公开(公告)号：US20170221965A1

    公开(公告)日：2017-08-03

    申请号：US15487743

    申请日：2017-04-14

    Applicant: Micron Technology, Inc.

    Inventor： Ugo Russo ,  Andrea Redaelli ,  Giorgio Servalli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

    Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.

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