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    Shared address counters for multiple modes of operation in a memory device
    113.
    发明授权
    Shared address counters for multiple modes of operation in a memory device 有权

    公开(公告)号：US10346244B2

    公开(公告)日：2019-07-09

    申请号：US15674178

    申请日：2017-08-10

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown

    IPC: G06F11/10 ,  G06F3/06

    Abstract: As described above, certain modes of operation, such as the Fast Zero mode and the ECS mode, may facilitate sequential access to individual cells of a memory array. To facilitate this functionality, a command controller may be provided, including one or more individual controllers to control the address sequencing when a particular mode entry command (e.g., Fast Zero or ECS) is received. In order to generate internal addresses to be accessed sequentially, one or more counters may also be provided. Advantageously, the counters may be shared such that they can be used in any mode of operation that may require address sequencing of all or large portions of the memory array, such as the Fast Zero mode or the ECS mode.

    METHODS AND APPARATUSES FOR REDUCING POWER CONSUMPTION IN A PATTERN RECOGNITION PROCESSOR
    114.
    发明申请
    METHODS AND APPARATUSES FOR REDUCING POWER CONSUMPTION IN A PATTERN RECOGNITION PROCESSOR 审中-公开

    公开(公告)号：US20190095497A1

    公开(公告)日：2019-03-28

    申请号：US16206290

    申请日：2018-11-30

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes ,  David R. Brown

    IPC: G06F17/30 ,  G06F1/32 ,  G06K9/00

    Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.

    SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING
    115.
    发明申请
    SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING 审中-公开

    公开(公告)号：US20190087360A1

    公开(公告)日：2019-03-21

    申请号：US16192509

    申请日：2018-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B. Noyes

    IPC: G06F13/12 ,  G06F13/40 ,  G06F13/28

    CPC classification number: G06F13/126 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/404 ,  G06F2213/2802

    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

    Methods and systems for data analysis in a state machine
    116.
    发明授权
    Methods and systems for data analysis in a state machine 有权

    公开(公告)号：US09870530B2

    公开(公告)日：2018-01-16

    申请号：US15262958

    申请日：2016-09-12

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown ,  Harold B Noyes

    IPC: G06F17/00 ,  G06N3/08 ,  G06K9/00 ,  G06N3/063

    CPC classification number: G06N3/08 ,  G06K9/00986 ,  G06N3/063

    Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.

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