公开(公告)号：US10769099B2

公开(公告)日：2020-09-08

申请号：US15534994

申请日：2015-12-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Paul D. Dlugosch

IPC: H04J3/04 ,  G06F15/78 ,  G06N20/00 ,  G06F9/448 ,  G06F1/3225 ,  G06F13/42 ,  G05B19/045 ,  G06F3/06

Abstract: A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line.

公开(公告)号：US10684983B2

公开(公告)日：2020-06-16

申请号：US15137877

申请日：2016-04-25

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F15/80 ,  H03K19/17728 ,  G06F16/903 ,  G06K9/00 ,  G06N5/00

Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.

公开(公告)号：US10606787B2

公开(公告)日：2020-03-31

申请号：US16519921

申请日：2019-07-23

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Inderjit S. Bains

IPC: G06F15/18 ,  G06F13/40 ,  G06F9/448 ,  G06F15/78 ,  G06N3/08

Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

公开(公告)号：US20190146937A1

公开(公告)日：2019-05-16

申请号：US16247244

申请日：2019-01-14

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Stephen P. King

IPC: G06F13/28 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/38 ,  G06F13/385 ,  G06F13/4004 ,  G06F13/4027

Abstract: Disclosed are methods and devices, among which is a device that uses a memory map to identify whether functionality of the device should be implemented. The device may be coupled to a separate device, and, in some embodiments, the device may determine and provide a response of the device to requests from the separate device.

公开(公告)号：US10019311B2

公开(公告)日：2018-07-10

申请号：US15280481

申请日：2016-09-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G11C13/00 ,  G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/1076 ,  H03M13/09

Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.

公开(公告)号：US20180089019A1

公开(公告)日：2018-03-29

申请号：US15280481

申请日：2016-09-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/1076 ,  H03M13/09

Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.

公开(公告)号：US09886017B2

公开(公告)日：2018-02-06

申请号：US15605542

申请日：2017-05-25

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G05B19/045 ,  G06F9/44 ,  G06F15/82 ,  G06F21/56 ,  H03K19/177 ,  G06N5/04

CPC classification number: G05B19/045 ,  G06F9/4498 ,  G06F15/82 ,  G06F21/567 ,  G06F2207/025 ,  G06N5/047 ,  H03K19/17724 ,  H03K19/17748

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

公开(公告)号：US09866218B2

公开(公告)日：2018-01-09

申请号：US15362232

申请日：2016-11-28

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Irene J. Xu

IPC: H03K19/177 ,  H03K19/20 ,  H03K19/21 ,  G06F9/44 ,  G05B19/045 ,  G06F17/50 ,  H03K19/0175 ,  G06F7/00

CPC classification number: H03K19/17708 ,  G05B19/045 ,  G06F7/00 ,  G06F9/4498 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/17704 ,  H03K19/20 ,  H03K19/21 ,  Y02T10/82

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

公开(公告)号：US09747242B2

公开(公告)日：2017-08-29

申请号：US15257677

申请日：2016-09-06

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Inderjit S. Bains

IPC: G06F17/00 ,  G06F13/40 ,  G06F15/78 ,  G06F9/44 ,  G06N3/08

CPC classification number: G06F13/4027 ,  G06F9/4498 ,  G06F15/7867 ,  G06N3/08

Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

公开(公告)号：US09734876B2

公开(公告)日：2017-08-15

申请号：US14599892

申请日：2015-01-19

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Mark Jurenka ,  Gavin Huggins

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C7/10 ,  G06F9/30 ,  G06F9/34 ,  G06F12/06

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/34 ,  G06F12/0615 ,  G06F2212/656

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.