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公开(公告)号：US20240038301A1
公开(公告)日：2024-02-01
申请号：US17877613
申请日：2022-07-29
Applicant: Micron Technology, Inc.
Inventor： Riccardo Muzzetto , Francesco Mastroianni , Ferdinando Bedeschi , Nevil N. Gajera
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0004 , G11C2013/0057
Abstract: Methods, systems, and devices for memory cell read operation techniques are described. A memory device may determine a starting voltage for a second phase of a read operation for a set of memory cells which may have a different magnitude than a magnitude of a starting voltage of a first phase of the read operation. For example, the memory device may use an ending voltage of the first phase to determine the starting voltage for the second phase. In some cases, the starting voltage for the second phase may correspond to a difference of a voltage offset and the ending voltage of the first phase. As part of the second phase of the read operation, the memory device may apply a sequence of voltages to the set of memory cells in accordance with the determined starting voltage of the second phase.
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公开(公告)号：US11869565B2
公开(公告)日：2024-01-09
申请号：US18056516
申请日：2022-11-17
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Umberto Di Vincenzo , Riccardo Muzzetto
CPC classification number: G11C11/2273 , G06F11/0727 , G06F11/0751 , G11C11/221 , G11C11/2259
Abstract: Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.
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公开(公告)号：US11842783B2
公开(公告)日：2023-12-12
申请号：US16976690
申请日：2020-03-03
Applicant: Micron Technology, Inc.
Inventor： Riccardo Muzzetto , Ferdinando Bedeschi , Umberto Di Vincenzo
CPC classification number: G11C29/46 , G11C29/1201 , G11C29/42
Abstract: Methods, systems, and devices related to counter-based sense amplifier method for memory cells are described. The counter-based read algorithm may comprise the following phases:
storing in a counter associated to an array of memory cells the value of the number of bits having a predetermined logic value of the data bits stored in the memory array;
reading from said counter the value corresponding to the number of bits having the predetermined logic value;
reading the data stored in the array of memory cells by applying a ramp of biasing voltages;
counting the number of bits having the predetermined logic value during the data reading phase;
stopping the data reading phase when the number of bits having the predetermined logic value is equal to the value stored in said counter.-
公开(公告)号：US11830536B2
公开(公告)日：2023-11-28
申请号：US17826979
申请日：2022-05-27
Applicant: Micron Technology, Inc.
Inventor： Riccardo Muzzetto
IPC: G11C11/22
CPC classification number: G11C11/2259 , G11C11/221 , G11C11/2257 , G11C11/2273 , G11C11/2275
Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.
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公开(公告)号：US11562790B1
公开(公告)日：2023-01-24
申请号：US17364029
申请日：2021-06-30
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Riccardo Muzzetto , Ferdinando Bedeschi
Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage at a first time duration to the memory array based on the read request. The control circuit is additionally configured to count a number of the plurality of memory cells that have switched to an active read state based on the first voltage and to derive a second time duration. The control circuit is further configured to apply a second voltage at the second duration to the memory array. The control circuit is also configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.
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Patent Agency Ranking
公开(公告)号：US20230005532A1
公开(公告)日：2023-01-05
申请号：US17364029
申请日：2021-06-30
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Riccardo Muzzetto , Ferdinando Bedeschi
IPC: G11C13/00
Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage at a first time duration to the memory array based on the read request. The control circuit is additionally configured to count a number of the plurality of memory cells that have switched to an active read state based on the first voltage and to derive a second time duration. The control circuit is further configured to apply a second voltage at the second duration to the memory array. The control circuit is also configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.
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公开(公告)号：US20220399055A1
公开(公告)日：2022-12-15
申请号：US17864004
申请日：2022-07-13
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Jeffrey E. Koelling , Hari Giduturi , Riccardo Muzzetto , Corrado Villa
IPC: G11C13/00
Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.
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公开(公告)号：US20220351784A1
公开(公告)日：2022-11-03
申请号：US17597004
申请日：2020-11-11
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Riccardo Muzzetto , Umberto Di Vincenzo
Abstract: The present disclosure relates to a method for accessing memory cells comprising: applying an increasing read voltage with a first polarity to the plurality of memory cells; counting a number of switching memory cells in the plurality based on the applying the increasing read voltage; applying a first read voltage with the first polarity based on the number of switched memory cells reaching a threshold number; applying a second read voltage with a second polarity opposite to the first polarity; and determining that a memory cell in the plurality of memory cells has a first logic value based on the memory cell having switched during one of the applying the increasing read voltage and the applying the first read voltage or based on the memory cell not having switched during the applying the second read voltage. A related system is also disclosed.
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公开(公告)号：US20220301622A1
公开(公告)日：2022-09-22
申请号：US17716716
申请日：2022-04-08
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Riccardo Muzzetto , Ferdinando Bedeschi
IPC: G11C13/00
Abstract: The present disclosure provides a method, a circuit, and a system for reading memory cells. The method may include: applying a first voltage with a first polarity to a plurality of the memory cells; applying a second voltage with a second polarity to one or more of said plurality of the memory cells; applying at least a third voltage with the first polarity to one or more of said plurality of the memory cells; detecting electrical responses of memory cells to the first voltage, the second voltage, and the third voltage; and determining a logic state of respective memory cells based on the electrical responses of the memory cells to the first voltage, the second voltage, and the third voltage.
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120.发明授权公开(公告)号：US11450358B2
公开(公告)日：2022-09-20
申请号：US17075502
申请日：2020-10-20
Applicant: Micron Technology, Inc.
Inventor： Riccardo Muzzetto , Ferdinando Bedeschi , Umberto Di Vincenzo
Abstract: The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.
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