公开(公告)号：US20110015897A1

公开(公告)日：2011-01-20

申请号：US12770738

申请日：2010-04-30

Applicant: SHEN-CHUN LI ,  SHOU-KUO HSU

Inventor： SHEN-CHUN LI ,  SHOU-KUO HSU

IPC: G06F15/00

CPC classification number: G01R31/2851

Abstract: A system and method for testing derating performance of a component obtains a component list, a pin list, and a standard derating list of the electronic device from a storage. The system and method further receives parameters of each component, the parameters of each component comprising voltages of two pins of the component and a working temperature of the component, calculates a working voltage and a derating ratio of the component according to the parameters. The system and method also analyzes the working voltage and the derating ratio of the component to get analysis result, generates a test report comprising the derating ratio, the working temperature, the analysis results of each component in the component list, and storing the test report in the storage.

Abstract translation: 用于测试部件的降额性能的系统和方法从存储器获得电子设备的组件列表，引脚列表和标准降额列表。 该系统和方法还接收每个组件的参数，每个组件的参数包括组件的两个引脚的电压和组件的工作温度，根据参数计算组件的工作电压和降额比。 该系统和方法还分析了组件的工作电压和降额比以获得分析结果，生成了包括降额比，工作温度，组件列表中每个组件的分析结果，以及存储测试报告的测试报告 在存储中。

公开(公告)号：US20100332169A1

公开(公告)日：2010-12-30

申请号：US12732201

申请日：2010-03-26

Applicant: HSIEN-CHUAN LIANG ,  SHEN-CHUN LI ,  SHOU-KUO HSU ,  YUNG-CHIEH CHEN

Inventor： HSIEN-CHUAN LIANG ,  SHEN-CHUN LI ,  SHOU-KUO HSU ,  YUNG-CHIEH CHEN

IPC: G01R27/16 ,  G06F19/00

CPC classification number: G01R31/2806 ,  G01R31/2805 ,  G01R31/281

Abstract: A method for testing a characteristic impedance of a signal path routing of a printed circuit board (PCB) controls the test device to test a characteristic impedance of the signal path routing of the PCB to get test data of the signal path routing of the PCB. The method further analyzes the test data of the signal path routing of the PCB get analysis results, generate a test report for storing the test data of each signal path routing of the PCB and the analysis results if all signal path routings of the PCB have been tested.

Abstract translation: 用于测试印刷电路板（PCB）的信号路径路由的特征阻抗的方法控制测试装置以测试PCB的信号路径路由的特性阻抗，以获得PCB的信号路径路由的测试数据。 该方法进一步分析了PCB获取分析结果的信号路径路由的测试数据，生成用于存储PCB的每个信号路径路由测试数据的测试报告和分析结果，如果PCB的所有信号路径布线已经被 测试。

公开(公告)号：US20100321910A1

公开(公告)日：2010-12-23

申请号：US12497709

申请日：2009-07-06

Applicant: SHOU-KUO HSU ,  CHUN-JEN CHEN

Inventor： SHOU-KUO HSU ,  CHUN-JEN CHEN

IPC: H05K7/00

CPC classification number: H05K1/0231 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/0969 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A printed circuit board includes a first signal layer, a first reference layer, a second reference layer, and a second signal layer. An integrated circuit mounted on the first signal layer includes a power supply terminal connected to a first power supply via. The second signal layer includes a filter and a power supply wire. The filter includes a power terminal connected to the first power supply via, and a ground terminal connected to the second reference layer. The first power supply via is connected to the first reference layer through the power supply wire and a second power supply via. A void defined in the second reference layer is at least partially vertically overlapping with the power supply wire, and enables the first reference layer to function as a reference plane for the power supply wire, to increase impedance of the power supply wire.

Abstract translation: 印刷电路板包括第一信号层，第一参考层，第二参考层和第二信号层。 安装在第一信号层上的集成电路包括连接到第一电源通孔的电源端子。 第二信号层包括滤波器和电源线。 滤波器包括连接到第一电源通孔的电源端子和连接到第二参考层的接地端子。 第一电源通孔通过电源线和第二电源通孔连接到第一参考层。 限定在第二参考层中的空隙至少部分地与电源线垂直重叠，并且使得第一参考层能够用作电源线的参考平面，以增加电源线的阻抗。

公开(公告)号：US20100276192A1

公开(公告)日：2010-11-04

申请号：US12503684

申请日：2009-07-15

Applicant: CHIA-NAN PAI ,  SHOU-KUO HSU

Inventor： CHIA-NAN PAI ,  SHOU-KUO HSU

IPC: H05K1/11 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K1/0251 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/09309 ,  H05K2201/096 ,  H05K2203/063 ,  Y10T29/49165

Abstract: A method for removing a stub of a via hole includes copperizing a wall of a via hole in a top layer of a printed circuit board (PCB) if signal lines are located on the top layer of the PCB, and a wall of the via hole in a bottom layer of the PCB is not copperized. The method further includes connecting the top layer and the bottom layer of the PCB using a connection layer.

Abstract translation: 用于去除通孔的短截线的方法包括如果信号线位于PCB的顶层上，则在印刷电路板（PCB）的顶层中的通孔的壁上铜化，并且通孔的壁 在PCB的底层没有铜化。 该方法还包括使用连接层连接PCB的顶层和底层。

公开(公告)号：US20100268498A1

公开(公告)日：2010-10-21

申请号：US12603666

申请日：2009-10-22

Applicant: SHEN-CHUN LI ,  SHOU-KUO HSU

Inventor： SHEN-CHUN LI ,  SHOU-KUO HSU

IPC: G01R13/00 ,  G06F19/00

CPC classification number: G01R31/2806

Abstract: A method for testing signals of electronic components. The method sends a positioning command to a control computer through a switch, so as to drive a probe holder of a mechanical arm to position probes of the oscilloscope on a position of the electronic component. The method further receives measured data collected by the oscilloscope, and compares the measured data with preset standard values to determine if the measured data is acceptable.

Abstract translation: 一种用于测试电子元件信号的方法。 该方法通过开关向控制计算机发送定位命令，以驱动机械臂的探头支架，将示波器的探针放置在电子部件的位置上。 该方法还接收示波器收集的测量数据，并将测量数据与预设的标准值进行比较，以确定测量数据是否可接受。

公开(公告)号：US20100258337A1

公开(公告)日：2010-10-14

申请号：US12430133

申请日：2009-04-27

Applicant: SHOU-KUO HSU ,  CHIA-NAN PAI

Inventor： SHOU-KUO HSU ,  CHIA-NAN PAI

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  H05K1/0253 ,  H05K1/0393 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0969

Abstract: A flexible printed circuit board (FPCB) includes a signal layer, upper and lower ground layers, and two dielectric layers. The signal layer includes a differential pair comprising two transmission lines to transmit a pair of differential signals. The dielectric layers are located on and under the signal layer to sandwich the signal layer. The upper ground layer is attached to the dielectric layer on the signal layer, opposite to the signal layer. The lower ground layer is attached to the dielectric layer under the signal layer, opposite to the signal layer. Each ground layer includes a grounded sheet made of conductive material. Two voids are defined in each ground layer and located at opposite sides of the corresponding grounded sheet. Distances between the middle line of the grounded sheet of each ground layer and middle lines of the two transmission lines are equal.

Abstract translation: 柔性印刷电路板（FPCB）包括信号层，上下接地层和两个电介质层。 信号层包括差分对，该差分对包括用于发送一对差分信号的两条传输线。 电介质层位于信号层之上和之下，以夹住信号层。 上层接地层与信号层的电介质层相连，与信号层相反。 下部接地层附着在与信号层相反的信号层下面的电介质层上。 每个接地层包括由导电材料制成的接地片。 在每个接地层中定义两个空隙，并且位于相应接地片的相对侧。 每个接地层的接地片的中间线与两条传输线的中间线之间的距离相等。

公开(公告)号：US20090242244A1

公开(公告)日：2009-10-01

申请号：US12126748

申请日：2008-05-23

Applicant: SHOU-KUO HSU ,  CHUN-JEN CHEN

Inventor： SHOU-KUO HSU ,  CHUN-JEN CHEN

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09336

Abstract: An exemplary PCB includes a first reference layer, a first signal layer, and a second signal layer in that order. A first differential pair is arranged in the first signal layer in an edge-coupled structure referencing the first reference layer. A second differential pair is arranged in the second signal layer in edge-coupled structure. A first ground part and a second ground part are symmetrically arranged at opposite sides of the second differential pair in the second signal layer. The first differential pair is arranged above the first ground part and a projection of the first differential pair onto the second signal layer having an area coincident with the first ground part. The second differential pair references the first and second ground parts.

Abstract translation: 示例性的PCB包括第一参考层，第一信号层和第二信号层。 第一差分对以参考第一参考层的边缘耦合结构布置在第一信号层中。 第二差分对以边缘耦合结构布置在第二信号层中。 第一接地部分和第二接地部分对称地布置在第二信号层中的第二差分对的相对侧。 第一差分对布置在第一接地部分的上方，并且第一差分对的突起与具有与第一接地部分重合的区域的第二信号层上。 第二差分对参考第一和第二接地部分。

公开(公告)号：US20090108956A1

公开(公告)日：2009-04-30

申请号：US11955409

申请日：2007-12-13

Applicant: SHOU-KUO HSU ,  HSIAO-CHUAN TU

Inventor： SHOU-KUO HSU ,  HSIAO-CHUAN TU

IPC: H03H7/48 ,  H03H7/38

CPC classification number: G06F13/4086

Abstract: A circuit topology for multiple loads includes a driving terminal, a first node coupled to the driving terminal and a second node via a first branch transmission line, a first receiving terminal which is a test point configured to detect errors of the circuit topology coupled to the first node via a second branch transmission line, a second and a third receiving terminal respectively coupled to the second node via a third branch transmission line and a fourth branch transmission line, wherein the difference between the length of the second branch transmitting line and that of the third branch transmitting line, and the difference between the length of the third branch transmitting line and that of the fourth branch transmitting line are greater than the product of a transmission speed and a rise time of the signal, and a first resistor is connected in the third branch transmission line.

Abstract translation: 用于多个负载的电路拓扑包括驱动终端，耦合到驱动终端的第一节点和经由第一分支传输线的第二节点，第一接收终端，其被配置为检测耦合到所述驱动终端的电路拓扑的错误 第一分支传输线，第二和第三接收终端，分别经由第三分支传输线和第四分支传输线耦合到第二节点，其中第二分支传输线的长度与 第三分支传输线，第三分支传输线的长度与第四分支传输线的长度之间的差大于传输速度和信号的上升时间的乘积，并且第一电阻器连接到 第三分支传输线。

公开(公告)号：US20090107716A1

公开(公告)日：2009-04-30

申请号：US11967017

申请日：2007-12-29

Applicant: YU-CHANG PAI ,  SHOU-KUO HSU ,  CHIEN-HUNG LIU

Inventor： YU-CHANG PAI ,  SHOU-KUO HSU ,  CHIEN-HUNG LIU

IPC: H05K1/11

CPC classification number: H05K1/0245 ,  H05K1/0228 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/09636 ,  H05K2201/097

Abstract: A printed circuit board (PCB) includes a differential pair having a first differential trace and a second differential trace, a first via having an upper cap and a lower cap, and a second via having an upper cap and a lower cap. The first differential trace includes a first segment and a second segment, the second differential trace includes a third segment and a fourth segment. The first and the third segments are electrically coupled to the upper caps of the first and the second vias respectively. The second and the fourth segments are electrically coupled to the lower caps of the first and the second vias respectively. The first and the third segments extend from corresponding upper caps in different directions, the second and the fourth segments extend from corresponding lower caps in different directions.

Abstract translation: 印刷电路板（PCB）包括具有第一差分迹线和第二差分迹线的差分对，具有上盖和下盖的第一通孔以及具有上盖和下盖的第二通孔。 第一差分迹线包括第一段和第二段，第二差分迹线包括第三段和第四段。 第一和第三段分别电耦合到第一和第二通孔的上盖。 第二和第四段分别电耦合到第一和第二通孔的下盖。 第一和第三段从相应的上盖在不同的方向上延伸，第二和第四段从相应的下盖在不同的方向延伸。

公开(公告)号：US20090089474A1

公开(公告)日：2009-04-02

申请号：US11954235

申请日：2007-12-12

Applicant: YING-TSO LAI ,  SHOU-KUO HSU

Inventor： YING-TSO LAI ,  SHOU-KUO HSU

IPC: G06F13/00

CPC classification number: G06F13/4072 ,  G06F13/4086 ,  G06F13/4234

Abstract: An exemplary motherboard for supporting different types of memory includes a driving module, a first slot, a second slot, and a transmission line connected the driving module, the first slot and the second slot in turn. The first slot is arranged for mounting a first type of memory. The second slot is arranged for mounting a second type of memory. The first memory and the second memory are alternatively mounted on the motherboard. The transmission line is grounded via a capacitor for eliminating echo signals generated by the first and second type memories. The motherboard for supporting different memory modes satisfies different type memories, and maintains integrality of signals transmitted therein.

Abstract translation: 用于支持不同类型存储器的示例性母板包括驱动模块，第一槽，第二槽和依次连接驱动模块，第一槽和第二槽的传输线。 第一个插槽用于安装第一种类型的存储器。 第二槽被安排用于安装第二类型的存储器。 第一存储器和第二存储器替代地安装在主板上。 传输线通过用于消除由第一和第二类型存储器产生的回波信号的电容器接地。 用于支持不同存储模式的主板满足不同类型的存储器，并且保持其中传输的信号的完整性。