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公开(公告)号：US06486078B1
公开(公告)日：2002-11-26
申请号：US09643531
申请日：2000-08-22
IPC分类号： H01L2131
CPC分类号： H01L21/0212 , H01L21/02203 , H01L21/02282 , H01L21/02343 , H01L21/31695
摘要： One aspect of the present invention relates to a method of forming a low k material layer on a semiconductor substrate, involving the steps of depositing a mixture containing a low k material and a casting solvent on the semiconductor substrate; optionally contacting the mixture with a transition solvent whereby the casting solvent is removed from the mixture to form a second mixture containing the low k material and the transition solvent; contacting the second mixture with a supercritical fluid whereby the transition solvent is removed from the second mixture; and permitting the supercritical fluid to evaporate thereby forming the low k material layer.
摘要翻译： 本发明的一个方面涉及在半导体衬底上形成低k材料层的方法，包括在半导体衬底上沉积含有低k材料和浇铸溶剂的混合物的步骤; 任选地将混合物与过渡溶剂接触，由此从混合物中除去浇注溶剂以形成含有低k材料和过渡溶剂的第二混合物; 使所述第二混合物与超临界流体接触，由此从所述第二混合物中除去所述过渡溶剂; 并允许超临界流体蒸发，从而形成低k材料层。
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公开(公告)号：US06451621B1
公开(公告)日：2002-09-17
申请号：US10050732
申请日：2002-01-16
IPC分类号： H01L2166
CPC分类号： H01L22/12
摘要： The present invention provides systems and methods wherein scatterometry is used to control an implant processes, such as an angled implant process. According to the invention, data relating to resist dimensions is obtained by scatterometry prior to an the implant process. The data is used to determine whether a resist is suitable for an implant process and/or determine an appropriate condition, such as an angle of implant or implantation dose, for an implant process.
摘要翻译： 本发明提供了系统和方法，其中使用散射法来控制植入过程，例如成角度的植入过程。 根据本发明，与抗蚀剂尺寸相关的数据通过在植入工艺之前的散射测量获得。 该数据用于确定抗蚀剂是否适合于植入过程，和/或确定用于植入过程的适当条件，例如植入角度或植入剂量。
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113.发明授权Deliberate void in innerlayer dielectric gapfill to reduce dielectric constant 有权内层介质间隙填料中的有意的空隙以降低介电常数公开(公告)号：US06445072B1
公开(公告)日：2002-09-03
申请号：US09617158
申请日：2000-07-17
IPC分类号： H01L214763
CPC分类号： H01L21/7682 , Y10S977/897
摘要： One aspect of the present invention relates to a method of forming an innerlayer dielectric, involving the steps of providing a substrate having at least two metal lines thereon; providing a conformal insulation layer over the substrate and metal lines; forming a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; at least one of thinning and planarizing the second insulation layer; and forming a third insulation layer over the second insulation layer. Another aspect of the present invention relates to an innerlayer dielectric semiconductor structure, containing a semiconductor substrate having at least two metal lines thereon; a conformal insulation layer over the semiconductor substrate and metal lines, the conformal insulation layer having a substantially uniform thickness from about 250 Å to about 5,000 Å; a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; and a third insulation layer over the second insulation layer.
摘要翻译： 本发明的一个方面涉及一种形成内层电介质的方法，包括以下步骤：提供其上具有至少两条金属线的基底; 在衬底和金属线上提供保形绝缘层; 在所述保形绝缘层上形成第二绝缘层，所述第二绝缘层包含位于两条金属线之间的空隙; 将所述第二绝缘层变薄和平坦化的至少一个; 以及在所述第二绝缘层上形成第三绝缘层。 本发明的另一方面涉及一种内层电介质半导体结构，其包含其上具有至少两条金属线的半导体衬底; 半导体衬底和金属线上的共形绝缘层，保形绝缘层具有从大约至大约等于的大致均匀的厚度; 在保形绝缘层之上的第二绝缘层，所述第二绝缘层包含位于两个金属线之间的空隙; 以及在所述第二绝缘层上的第三绝缘层。
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公开(公告)号：US06422918B1
公开(公告)日：2002-07-23
申请号：US09478118
申请日：2000-01-04
IPC分类号： B24B4900
CPC分类号： H01L21/0273 , G03F7/168 , G03F7/3021 , H01L21/31058
摘要： The present invention relates to a system for controllably removing photoresist. A CMP system is employed for polishing the photoresist. A non-abrasive polishing liquid adapted to react with the photoresist to sufficiently modify bonding in the photoresist is employed to facilitate surface layer removal of the photoresist by applied mechanical stress from the CMP system.
摘要翻译： 本发明涉及可控制地除去光致抗蚀剂的系统。 使用CMP系统来抛光光致抗蚀剂。 采用适于与光致抗蚀剂反应以充分改善光致抗蚀剂中的结合的非磨料抛光液，以便通过来自CMP系统的应力机械应力促进光致抗蚀剂的表面层去除。
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公开(公告)号：US06413857B1
公开(公告)日：2002-07-02
申请号：US09824349
申请日：2001-04-02
IPC分类号： H01L214763
CPC分类号： H01L29/66772 , H01L21/743 , H01L21/84 , H01L29/78612 , H01L29/78645 , H01L29/78648
摘要： An SOI device structure is provided which facilitates mitigation of charge build up caused by floating body effects. A plurality of local interconnects are formed from a top insulating layer to a top silicon layer of the SOI device structure. A ground contact is then formed from the top insulating layer to a bottom substrate layer of the SOI device structure. The ground contact extends through the insulating layer, an isolation region and an oxide layer to the bottom substrate layer.
摘要翻译： 提供了SOI器件结构，其有助于减轻由浮体效应引起的电荷积累。 多个局部互连由SOI器件结构的顶部绝缘层到顶部硅层形成。 然后从顶部绝缘层到SOI器件结构的底部基底层形成接地触点。 接地触头延伸穿过绝缘层，隔离区域和氧化物层延伸到底部基底层。
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公开(公告)号：US06358843B1
公开(公告)日：2002-03-19
申请号：US09824421
申请日：2001-04-02
申请人： Carl P. Babcock , Bhanwar Singh
发明人： Carl P. Babcock , Bhanwar Singh
IPC分类号： H01L214763
CPC分类号： G03F7/203 , H01L21/0274 , H01L21/31144 , H01L21/76802
摘要： A method of fabricating ultra small vias in insulating layers on a semiconductor substrate for an integrated circuit by a first exposure of a photoresist to line pattern with the semiconductor substrate in a first position and the exposure dosage being insufficient to develop the photoresist followed by a second overlapping exposure of the line pattern with the semiconductor substrate being in a position 90° from the first position and again being insufficient in exposure dosage to develop the photoresist, the overlapped line exposures creating via exposures of sufficient dosage to develop the photoresist, thereby creating a smaller via opening than with a single exposure.
摘要翻译： 一种在半导体衬底上用于集成电路的绝缘层中的超小通孔的制造方法，该方法是通过在第一位置首先将半导体衬底的光致抗蚀剂曝光到线图案，并且曝光剂量不足以显影光致抗蚀剂，然后是第二 线路图案与半导体衬底的重叠曝光处于距离第一位置90°的位置，并且曝光用量不足以显影光致抗蚀剂，通过曝光足够的剂量产生重叠的线暴露以显影光致抗蚀剂，由此产生 通过开口比单次曝光更小。
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公开(公告)号：US06352817B1
公开(公告)日：2002-03-05
申请号：US09422592
申请日：1999-10-21
IPC分类号： G03C500
CPC分类号： H01L21/0274 , G03F7/38
摘要： The present invention relates to a method for mitigating T-tops and/or stringers and/or crusts in a structure. A photoresist layer of the structure is exposed. The structure further includes an underlayer under the photoresist layer, and a substrate under the underlayer. A chemical mechanical polishing process is employed to remove a predetermined thickness of the photoresist layer. An underlayer etch is performed to remove select portions of the underlayer.
摘要翻译： 本发明涉及一种用于减轻结构中的T形顶和/或桁条和/或外壳的方法。 曝光该结构的光致抗蚀剂层。 该结构还包括光致抗蚀剂层下的底层和底层下的基底。 采用化学机械抛光工艺去除光致抗蚀剂层的预定厚度。 执行底层蚀刻以去除底层的选择部分。
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公开(公告)号：US06262484B1
公开(公告)日：2001-07-17
申请号：US09295812
申请日：1999-04-20
IPC分类号： H01L23485
CPC分类号： H01L21/76807
摘要： A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.
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公开(公告)号：US06255202B1
公开(公告)日：2001-07-03
申请号：US09619836
申请日：2000-07-20
IPC分类号： H01L213205
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/28123 , H01L21/76807 , H01L29/4238 , H01L29/4925
摘要： A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating layer over the gate oxide layer. An opening is formed extending partially into the insulating layer. The opening in the insulating layer extends from a top surface of the insulating layer to a first depth. Spacers are then formed on the sides of the opening. The opening is then extended in the insulating layer from the first depth to a second depth. The opening is wider from the top surface of the insulating layer to the first depth than the opening is from the first depth to the second depth. The spacers are then removed from the opening. The opening is then filled with a conductive material to form a T-gate structure.
摘要翻译： 提供了一种制造T型栅结构的方法。 提供一种结构，其具有硅层，该硅层具有栅极氧化物层，栅极氧化物层上的多晶硅层和栅极氧化物层上的绝缘层。 形成部分地延伸到绝缘层中的开口。 绝缘层中的开口从绝缘层的顶表面延伸到第一深度。 然后在开口的两侧形成隔板。 然后将开口在绝缘层中从第一深度延伸到第二深度。 开口从绝缘层的顶表面到比第一深度从第一深度到第二深度的第一深度更宽。 然后将隔离物从开口中取出。 然后用导电材料填充开口以形成T形栅结构。
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120.发明授权Antireflective coating used in the fabrication of microcircuit structures in 0.18 micron and smaller technologies 有权用于制造0.18微米和更小技术的微电路结构的抗反射涂层
公开(公告)号：US6165855A
公开(公告)日：2000-12-26
申请号：US205068
申请日：1998-12-04
申请人： Paul R. Besser , Bhanwar Singh , Darrell M. Erb , Susan H. Chen , Carmen Morales
发明人： Paul R. Besser , Bhanwar Singh , Darrell M. Erb , Susan H. Chen , Carmen Morales
IPC分类号： G03F7/09 , H01L21/027 , H01L21/28 , H01L21/3213 , H01L21/768 , H01L21/8238
CPC分类号： H01L21/7685 , G03F7/091 , H01L21/0276 , H01L21/28061 , H01L21/28123 , H01L21/32139 , H01L21/76885 , H01L2221/1078
摘要： An anti-reflective coating for use in microcircuit fabrication and specifically using ultraviolet photolithographic processes. A three layered anti-reflective coating is used to enhance metallization etching in the construction of microcircuits. The coating features a titanium nitride anti-reflective layer sandwiched between two titanium metal layers. The upper titanium layer protects subsequently applied deep ultraviolet photoresists from the deleterious effects of the titanium nitride anti-reflective layer. The unique character of the three layer anti-reflective coating allows the use of an efficient single chamber fabrication process to form the three layer coating.
摘要翻译： 用于微电路制造的抗反射涂层，特别是使用紫外光刻工艺。 三层抗反射涂层用于增强微电路结构中的金属化蚀刻。 该涂层具有夹在两个钛金属层之间的氮化钛抗反射层。 上钛层保护随后施加的深紫外光致抗蚀剂免受氮化钛抗反射层的有害影响。 三层抗反射涂层的独特特征允许使用有效的单室制造工艺来形成三层涂层。
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