公开(公告)号：US20060151430A1

公开(公告)日：2006-07-13

申请号：US11358393

申请日：2006-02-21

申请人： Hui Yang ,  Miao-Ju Hsu ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Hui Yang ,  Miao-Ju Hsu ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： G01L21/30 ,  G01R31/00

CPC分类号： H01L21/31116 ,  H01J37/32935 ,  H01L22/26

摘要： A method of processing multi-layer films, the method including: (1) processing a plurality of layers according to selected parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during the processing of the associated one of the plurality of layers, and (3) determining dynamic processing progressions each based on one of the plurality of optical characteristics that is associated with a particular one of the plurality of layers undergoing the processing.

摘要翻译： 一种处理多层薄膜的方法，该方法包括：（1）根据选定的参数处理多个层，（2）确定多个光学特性，每个光学特性与多个层之一相关联，并在处理过程中确定 所述多个层中的相关联的一个层，以及（3）基于与经历所述处理的所述多个层中的特定一个层相关联的所述多个光学特性中的一个来确定动态处理进度。

公开(公告)号：US20060118878A1

公开(公告)日：2006-06-08

申请号：US11003844

申请日：2004-12-02

申请人： Yi-Chun Huang ,  Hun-Jan Tao ,  Chun-Chieh Lin ,  Chih-Hsin Ko

发明人： Yi-Chun Huang ,  Hun-Jan Tao ,  Chun-Chieh Lin ,  Chih-Hsin Ko

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L29/165 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： An NMOS and PMOS device pair having a selected stress level and type exerted on a respective channel region and method for forming the same, the method including providing a semiconductor substrate; forming isolation regions to separate active areas comprising a PMOS device region and an NMOS device region; lithographically patterning the semiconductor substrate and etching respective recessed areas including the respective NMOS and PMOS device regions into the silicon semiconductor substrate to a predetermined depth; backfilling the respective recessed areas with at least one semiconductor alloy; and, forming gate structures and offset spacers over the respective NMOS and PMOS device regions.

摘要翻译： 具有选择的应力水平和施加在相应沟道区上的类型的NMOS和PMOS器件对及其形成方法，所述方法包括提供半导体衬底; 形成隔离区以分离包括PMOS器件区和NMOS器件区的有源区; 将半导体衬底光刻图形化并将包括各个NMOS和PMOS器件区域的各个凹陷区域蚀刻到硅半导体衬底中至预定深度; 用至少一种半导体合金回填相应的凹陷区域; 以及在各个NMOS和PMOS器件区域上形成栅极结构和偏置间隔物。

公开(公告)号：US20060073620A1

公开(公告)日：2006-04-06

申请号：US10949037

申请日：2004-09-24

申请人： Jyu-Horng Shieh ,  Wen-Chih Chiou ,  Peng-Fu Hsu ,  Baw-Ching Perng ,  Hun-Jan Tao ,  Chin-Jen Chen

发明人： Jyu-Horng Shieh ,  Wen-Chih Chiou ,  Peng-Fu Hsu ,  Baw-Ching Perng ,  Hun-Jan Tao ,  Chin-Jen Chen

IPC分类号： H01L21/66

CPC分类号： H01L22/34

摘要： Methods and structures for critical dimension or profile measurement are disclosed. The method provides a substrate having periodic openings therein. Material layers are formed in the openings, substantially planarizing a surface of the substrate. A scattering method is applied to the substrate with the material layers for critical dimension (CD) or profile measurement.

摘要翻译： 公开了关键尺寸或轮廓测量的方法和结构。 该方法提供其中具有周期性开口的基板。 在开口中形成材料层，基本上平坦化基底的表面。 将散射方法应用于具有临界尺寸（CD）或轮廓测量的材料层的基底。

公开(公告)号：US07022610B2

公开(公告)日：2006-04-04

申请号：US10743979

申请日：2003-12-22

申请人： Chun-Li Chou ,  Yih-Ann Lin ,  Yi-Chen Huang ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Chun-Li Chou ,  Yih-Ann Lin ,  Yi-Chen Huang ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/302

CPC分类号： H01L21/02071 ,  H01L21/02063 ,  H01L21/76807

摘要： A method for cleaning semiconductor substrates includes a DI water clean operation that uses a spin speed no greater than 350 rpm. The cleaning method may include additional cleaning operations such as an organic clean, an aqueous chemical clean or a DI water/ozone clean. The cleaning method may be used to clean substrates after the conclusion of an etching procedure which exposes a single film between a Cu-containing conductive material and the environment. The spin speed of the DI water clean operation prevents copper corrosion due to breakdown of the film that separates the Cu-containing conductive material from the environment.

摘要翻译： 用于清洁半导体衬底的方法包括使用不大于350rpm的旋转速度的去离子水清洁操作。 清洁方法可以包括附加的清洁操作，例如有机清洁剂，水性化学清洁剂或去离子水/臭氧清洁剂。 在完成了在含Cu导电材料和环境之间暴露单个膜的蚀刻过程结束之前，清洁方法可用于清洁衬底。 去离子水清洁操作的旋转速度可防止由于将含Cu导电材料与环境分离的膜破裂导致铜腐蚀。

公开(公告)号：US20050274393A1

公开(公告)日：2005-12-15

申请号：US10866325

申请日：2004-06-09

申请人： Baw-Ching Perng ,  Hun-Jan Tao

发明人： Baw-Ching Perng ,  Hun-Jan Tao

IPC分类号： B08B3/02 ,  B08B3/04 ,  B08B7/00 ,  C23G1/00 ,  H01L21/00 ,  H01L21/02

CPC分类号： H01L21/02063 ,  B08B3/02 ,  B08B3/04 ,  H01L21/67051

摘要： A novel process for cleaning a semiconductor wafer is disclosed. The process of the invention reduces or eliminates charge-up damage caused by friction which is generated between the wafer and rinsing water or other fluid as the wafer is rotated during the cleaning process. In one embodiment of the invention, the wafer is placed on a rotatable chuck or support inside a cleaning chamber. An ion-forming gas is introduced into the chamber as the cleaning fluid is dispensed onto the wafer. The gas increases the electrical conductivity of the cleaning fluid by forming ions in the fluid, thereby reducing or eliminating cleaning fluid charge-up and preventing breakdown of dielectric materials and/or corrosion of metal on the wafer. In another embodiment, the gas is dissolved in the cleaning fluid, which is dispensed on the rotating wafer. In still another embodiment, the cleaning fluid is heated and then dispensed onto the wafer.

摘要翻译： 公开了一种用于清洁半导体晶片的新颖方法。 本发明的方法降低或消除了在清洁过程中晶片旋转时在晶片和漂洗水或其它流体之间产生的由摩擦产生的充电损伤。 在本发明的一个实施例中，将晶片放置在清洁室内的可旋转卡盘或支撑件上。 当清洁流体被分配到晶片上时，离子形成气体被引入到腔室中。 该气体通过在流体中形成离子来增加清洁流体的导电性，从而减少或消除清洁液充注并防止电介质材料的破坏和/或晶片上金属的腐蚀。 在另一个实施方案中，气体溶解在分配在旋转晶片上的清洁流体中。 在另一个实施例中，将清洁流体加热然后分配到晶片上。

公开(公告)号：US20050253204A1

公开(公告)日：2005-11-17

申请号：US10846278

申请日：2004-05-13

申请人： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/44 ,  H01L29/40

CPC分类号： H01L29/66507 ,  H01L21/28097

摘要： A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

摘要翻译： 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

公开(公告)号：US20050064721A1

公开(公告)日：2005-03-24

申请号：US10667013

申请日：2003-09-19

申请人： Ming-Huan Tsai ,  Ru-Chian Chiang ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Ru-Chian Chiang ,  Hun-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/60

CPC分类号： H01L21/76897 ,  H01L21/31105 ,  H01L21/31116

摘要： A new method for fabricating a borderless interconnection in a semiconductor device is provided. During fabrication, the device includes an interlevel dielectric (ILD) layer, a metal silicide layer, and a stop layer disposed between the ILD and metal silicide layers. The stop layer may be formed of silicon nitride or silicon oxynitride, and the metal silicide layer may be a nickel silicide. The method includes etching the ILD layer to expose at least a portion of the stop layer and then performing a nitrogen plasma treatment on the exposed portion of the stop layer. After the treatment, the exposed portion of the stop layer is removed to provide the interconnection hole. Because of the plasma treatment, damage to the metal silicide underlying the stop layer will be minimized when the stop layer is removed.

摘要翻译： 提供了一种在半导体器件中制造无边界互连的新方法。 在制造期间，器件包括层间电介质（ILD）层，金属硅化物层和设置在ILD和金属硅化物层之间的阻挡层。 阻挡层可以由氮化硅或氮氧化硅形成，并且金属硅化物层可以是硅化镍。 该方法包括蚀刻ILD层以暴露停止层的至少一部分，然后在停止层的暴露部分上进行氮等离子体处理。 在处理之后，去除停止层的暴露部分以提供互连孔。 由于等离子体处理，当停止层被去除时，对停止层下面的金属硅化物的损坏将被最小化。

公开(公告)号：US06828205B2

公开(公告)日：2004-12-07

申请号：US10072798

申请日：2002-02-07

申请人： Ming-Huan Tsai ,  Ming-Jie Huang ,  Huan-Just Lin ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Ming-Jie Huang ,  Huan-Just Lin ,  Hun-Jan Tao

IPC分类号： H01L218222

CPC分类号： H01L21/31111 ,  H01L21/28123 ,  H01L21/32139

摘要： A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of the substrate for forming a semiconductor feature according to an anisotropic plasma etching process; isotropically wet etching the hard mask to reduce a dimension of the hard mask prior to carrying out the anisotropic plasma etching process; and, anisotropically plasma etching a portion of the substrate not covered by the hard mask to form the semiconductor feature.

摘要翻译： 一种使用各向同性湿蚀刻工艺化学工艺的方法，用于修整具有改进的临界尺寸控制的半导体特征尺寸，包括提供覆盖在半导体晶片中的衬底的硬掩模，所述硬掩模被图案化以掩蔽用于形成半导体特征的衬底的一部分 根据各向异性等离子体蚀刻工艺; 在进行各向异性等离子体蚀刻工艺之前，均匀地湿式蚀刻硬掩模以减小硬掩模的尺寸; 并且各向异性等离子体蚀刻未被硬掩模覆盖的衬底的一部分以形成半导体特征。

公开(公告)号：US06794230B2

公开(公告)日：2004-09-21

申请号：US10284963

申请日：2002-10-31

申请人： Ming-Jie Huang ,  Hun-Jan Tao

发明人： Ming-Jie Huang ,  Hun-Jan Tao

IPC分类号： H01L2184

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/32139 ,  Y10S430/151

摘要： A process is described for transferring a photoresist pattern into a substrate. In one embodiment a stack comprised of a top photoresist layer, a middle ARC layer, and a bottom hardmask is formed over a gate electrode layer. A line in the photoresist pattern is anisotropically transferred through the ARC and hardmask. Then an isotropic etch to trim the linewidth by 0 to 50 nm per edge is performed simultaneously on the photoresist, ARC and hardmask. This method minimizes the amount of line end shortening to less than three times the dimension trimmed from one line edge. Since a majority of the photoresist layer is retained, the starting photoresist thickness can be reduced by 1000 Angstroms or more to increase process window. The pattern is then etched through the underlying layer to form a gate electrode. The method can also be used to form STI features in a substrate.

摘要翻译： 描述了将光致抗蚀剂图案转印到基底中的方法。 在一个实施例中，在栅极电极层上形成由顶部光致抗蚀剂层，中间ARC层和底部硬掩模构成的堆叠。 光刻胶图案中的一条线通过ARC和硬掩模各向异性传输。 然后，在光致抗蚀剂，ARC和硬掩模上同时进行各向同性蚀刻，以将每条边缘的线宽修剪0至50nm。 该方法将线端缩短的量最小化为小于从一条线边缘修剪的尺寸的三倍。 由于保留了光致抗蚀剂层的大部分，所以起始光致抗蚀剂的厚度可以减小1000埃以上，以增加工艺窗口。 然后通过下面的层蚀刻图案以形成栅电极。 该方法也可用于在基底中形成STI特征。

公开(公告)号：US06764911B2

公开(公告)日：2004-07-20

申请号：US10143227

申请日：2002-05-10

申请人： Jw-Wang Hsu ,  Ming-Huan Tsai ,  Mei-Ru Kuo ,  Baw-Ching Peng ,  Hun-Jan Tao

发明人： Jw-Wang Hsu ,  Ming-Huan Tsai ,  Mei-Ru Kuo ,  Baw-Ching Peng ,  Hun-Jan Tao

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Within a method for forming a spacer layer from a second layer formed of a second material laminated upon a first layer formed of a first material, in turn formed over a topographic feature, there is employed a three step etch method. The three step etch method employs: (1) a first etch method having a first enhanced etch selectivity for the second material with respect to the first material; (2) a second etch method having a second substantially neutral etch selectivity for the second material with respect to the first material; and (3) a third etch method having a third enhanced etch selectivity for the first material with respect to the second material. In accord with the three step etch method, the spacer layer is fabricated with enhanced dimensional control.

摘要翻译： 在由层压在由第一材料形成的第一层上的第二材料形成的第二层形成间隔层的方法中，依次形成在地形特征上，采用三步骤蚀刻方法。 三步骤蚀刻方法采用：（1）第一蚀刻方法相对于第一材料具有对第二材料的第一增强蚀刻选择性; （2）对于第二材料相对于第一材料具有第二基本中性蚀刻选择性的第二蚀刻方法; 和（3）第三蚀刻方法，其相对于第二材料具有第一材料的第三增强蚀刻选择性。 根据三步蚀刻方法，间隔层用增强的尺寸控制制造。