公开(公告)号：US20130043466A1

公开(公告)日：2013-02-21

申请号：US13572847

申请日：2012-08-13

申请人： Masafumi NOMURA ,  Kenichi OKAZAKI ,  Toshiyuki MIYAMOTO ,  Takashi HAMOCHI ,  Shunpei YAMAZAKI

发明人： Masafumi NOMURA ,  Kenichi OKAZAKI ,  Toshiyuki MIYAMOTO ,  Takashi HAMOCHI ,  Shunpei YAMAZAKI

IPC分类号： H01L29/786 ,  H01L21/42

CPC分类号： H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78693

摘要： A semiconductor device including an oxide semiconductor and including a more excellent gate insulating film is provided. A highly reliable and electrically stable semiconductor device having a small number of changes in the film structure, the process conditions, the manufacturing apparatus, or the like from a mass production technology that has been put into practical use is provided. A method for manufacturing the semiconductor device is provided. The semiconductor device includes a gate electrode, a gate insulating film formed over the gate electrode, and an oxide semiconductor film formed over the gate insulating film. The gate insulating film includes a silicon nitride oxide film, a silicon oxynitride film formed over the silicon nitride oxide film, and a metal oxide film formed over the silicon oxynitride film. The oxide semiconductor film is formed over and in contact with the metal oxide film.

摘要翻译： 提供了包括氧化物半导体并且包括更优异的栅极绝缘膜的半导体器件。 本发明提供了一种从投入实际使用的大规模生产技术的膜结构，工艺条件，制造装置等的变化少的高可靠性和电稳定性的半导体装置。 提供一种半导体器件的制造方法。 半导体器件包括形成在栅电极上的栅电极，栅绝缘膜和形成在栅极绝缘膜上的氧化物半导体膜。 栅极绝缘膜包括在氮氧化硅膜上形成的氮氧化硅膜，氧氮化硅膜和在氧氮化硅膜上形成的金属氧化物膜。 氧化物半导体膜形成在金属氧化物膜上并与其接触。

公开(公告)号：US20130011962A1

公开(公告)日：2013-01-10

申请号：US13603484

申请日：2012-09-05

申请人： Shunpei YAMAZAKI ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Hitomi SATO ,  Masahiro WATANABE ,  Mitsuo MASHIYAMA ,  Kenichi OKAZAKI ,  Motoki NAKASHIMA ,  Takashi SHIMAZU

发明人： Shunpei YAMAZAKI ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Hitomi SATO ,  Masahiro WATANABE ,  Mitsuo MASHIYAMA ,  Kenichi OKAZAKI ,  Motoki NAKASHIMA ,  Takashi SHIMAZU

IPC分类号： H01L21/363 ,  C23C14/08 ,  C23C14/34

CPC分类号： C23C14/08 ,  B28B11/243 ,  C04B35/453 ,  C04B35/64 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/76 ,  C23C14/086 ,  C23C14/3414 ,  C23C14/345 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869

摘要： There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.

摘要翻译： 已经有使用氧化物半导体形成的晶体管的可靠性与使用非晶硅形成的晶体管的可靠性差。 因此，在本发明中，制造了包括使用氧化物半导体形成的高可靠性晶体管的半导体器件。 使用包含具有结晶性的氧化物半导体的溅射靶，通过溅射法沉积氧化物半导体膜，并且其中晶体的c轴方向平行于氧化物半导体的顶表面的法向矢量。 通过混合原料形成靶，使其组成比可以得到晶体结构。

公开(公告)号：US20120298998A1

公开(公告)日：2012-11-29

申请号：US13473653

申请日：2012-05-17

申请人： Shunpei YAMAZAKI ,  Masahiro WATANABE ,  Mitsuo MASHIYAMA ,  Kenichi OKAZAKI ,  Motoki NAKASHIMA ,  Hideyuki KISHIDA

发明人： Shunpei YAMAZAKI ,  Masahiro WATANABE ,  Mitsuo MASHIYAMA ,  Kenichi OKAZAKI ,  Motoki NAKASHIMA ,  Hideyuki KISHIDA

IPC分类号： H01L29/786 ,  H01L21/20

CPC分类号： H01L21/02631 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869

摘要： The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.

摘要翻译： 氧化物半导体膜中的杂质浓度降低，可以获得高可靠性。

公开(公告)号：US20110260285A1

公开(公告)日：2011-10-27

申请号：US13177585

申请日：2011-07-07

申请人： Shunpei YAMAZAKI ,  Mitsuhiro ICHIJO ,  Makoto FURUNO ,  Takashi OHTSUKI ,  Kenichi OKAZAKI ,  Tetsuhiro TANAKA ,  Seiji YASUMOTO

发明人： Shunpei YAMAZAKI ,  Mitsuhiro ICHIJO ,  Makoto FURUNO ,  Takashi OHTSUKI ,  Kenichi OKAZAKI ,  Tetsuhiro TANAKA ,  Seiji YASUMOTO

IPC分类号： H01L29/06

CPC分类号： H01L21/76254 ,  H01L21/84

摘要： To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH4 and N2O as source gases is in contact with the single-crystal semiconductor layer.

摘要翻译： 为了提供包括适用于实际使用的结晶半导体层的半导体衬底，以及使用与半导体层的材料不同的材料用于支撑衬底，以及使用该半导体衬底的半导体器件。 半导体基板包括形成接合面的接合层，由含氮的绝缘材料形成的阻挡层，由包含小于20at的氮的绝缘材料形成的凸版层。 ％和氢气在1 at。 ％至20 at。 ％，以及含有卤素的绝缘层，在支撑基板和单晶半导体层之间。 半导体器件至少部分地包括上述结构，并且通过使用SiH 4和N 2 O作为源气体的微波等离子体CVD方法形成的栅极绝缘层与单晶半导体层接触。

公开(公告)号：US20130069055A1

公开(公告)日：2013-03-21

申请号：US13608044

申请日：2012-09-10

申请人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Hiromachi GODO ,  Takehisa HATANO ,  Sachiaki TEZUKA ,  Suguru HONDO ,  Naoto YAMADE ,  Junichi KOEZUKA

发明人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Hiromachi GODO ,  Takehisa HATANO ,  Sachiaki TEZUKA ,  Suguru HONDO ,  Naoto YAMADE ,  Junichi KOEZUKA

IPC分类号： H01L29/78

CPC分类号： H01L29/41733 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693

摘要： Provided is a semiconductor device in which an oxide semiconductor layer is provided; a pair of wiring layers which are provided with the gate electrode layer interposed therebetween are electrically connected to the low-resistance regions; and electrode layers are provided to be in contact with the low-resistance regions, below regions where the wiring layers are formed.

摘要翻译： 提供一种半导体器件，其中提供氧化物半导体层; 设置有栅极电极层的一对布线层电连接到低电阻区域; 并且电极层设置成与低电阻区域接触，在形成布线层的区域之下。

公开(公告)号：US20130062607A1

公开(公告)日：2013-03-14

申请号：US13604669

申请日：2012-09-06

申请人： Shunpei YAMAZAKI ,  Jun Koyama

发明人： Shunpei YAMAZAKI ,  Jun Koyama

IPC分类号： H01L29/786

CPC分类号： H01L27/1225 ,  H01L27/0266

摘要： A protection circuit for efficiently reducing the influence of ESD and a semiconductor device in which the influence of ESD is efficiently reduced are provided. The protection circuit includes at least two protection diodes. Each protection diode is a transistor including two gates facing each other with a semiconductor layer in which a channel is formed sandwiched between the gates. A fixed potential is applied to one of the gates of the transistor.

摘要翻译： 提供了用于有效降低ESD的影响的保护电路和其中有效降低ESD的影响的半导体器件。 保护电路包括至少两个保护二极管。 每个保护二极管是包括两个彼此面对的栅极的晶体管，半导体层中形成夹在栅极之间的沟道。 固定电位施加到晶体管的一个栅极。

公开(公告)号：US20130009209A1

公开(公告)日：2013-01-10

申请号：US13535506

申请日：2012-06-28

申请人： Shunpei YAMAZAKI

发明人： Shunpei YAMAZAKI

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/7782 ,  H01L29/78603 ,  H01L29/78696

摘要： To provide a transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use and provide a semiconductor device including the transistor, in a transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating film, and a gate electrode are stacked in this order over an oxide semiconductor insulating film, an oxide semiconductor stack layer which includes at least two oxide semiconductor layers with energy gaps different from each other and a mixed region therebetween is used as the semiconductor layer.

摘要翻译： 为了提供一种包括氧化物半导体层并且具有根据预期用途需要的电特性的晶体管，并且在包括半导体层，源极和漏极电极层，栅极绝缘膜和 栅电极依次堆叠在氧化物半导体绝缘膜上，氧化物半导体堆叠层，其包括具有彼此不同的能隙的至少两个氧化物半导体层以及它们之间的混合区域作为半导体层。

公开(公告)号：US20130001583A1

公开(公告)日：2013-01-03

申请号：US13609906

申请日：2012-09-11

申请人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Jun KOYAMA ,  Yukio TANAKA ,  Hidehito KITAKADO ,  Hideto OHNUMA

发明人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Jun KOYAMA ,  Yukio TANAKA ,  Hidehito KITAKADO ,  Hideto OHNUMA

IPC分类号： H01L29/786

CPC分类号： G02F1/1368 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2201/123 ,  G02F2202/104 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/458 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L2029/7863 ,  H01L2227/323

摘要： This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

公开(公告)号：US20130001568A1

公开(公告)日：2013-01-03

申请号：US13609915

申请日：2012-09-11

申请人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Jun KOYAMA ,  Yukio TANAKA ,  Hidehito KITAKADO ,  Hideto OHNUMA

发明人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Jun KOYAMA ,  Yukio TANAKA ,  Hidehito KITAKADO ,  Hideto OHNUMA

IPC分类号： H01L29/786

CPC分类号： G02F1/1368 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2201/123 ,  G02F2202/104 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/458 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L2029/7863 ,  H01L2227/323

摘要： This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

摘要翻译： 本发明提供一种具有高操作性能和高可靠性的半导体器件。 在形成驱动电路的n沟道TFT 802中配置与栅极配线重叠的LDD区域707，能够实现高耐热载流子注入的TFT结构。 不与栅极布线重叠的LDD区域717,718,719和720被布置在形成像素单元的n沟道TFT 804中。 结果，实现了具有小的截止电流值的TFT结构。 在这种情况下，属于周期表第15族的元素在LDD区707中比在LDD区717,718,719和720中的浓度更高。

公开(公告)号：US20120319183A1

公开(公告)日：2012-12-20

申请号：US13495313

申请日：2012-06-13

申请人： Shunpei YAMAZAKI ,  Tatsuya HONDA

发明人： Shunpei YAMAZAKI ,  Tatsuya HONDA

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L29/045 ,  H01L29/24 ,  H01L29/267 ,  H01L29/7782 ,  H01L29/78609 ,  H01L29/78696

摘要： One object of the present invention is to provide a structure of a transistor including an oxide semiconductor in a channel formation region in which the threshold voltage of electric characteristics of the transistor can be positive, which is a so-called normally-off switching element, and a manufacturing method thereof. A second oxide semiconductor layer which has greater electron affinity and a smaller energy gap than a first oxide semiconductor layer is formed over the first oxide semiconductor layer. Further, a third oxide semiconductor layer is formed to cover side surfaces and a top surface of the second oxide semiconductor layer, that is, the third oxide semiconductor layer covers the second oxide semiconductor layer.

摘要翻译： 本发明的一个目的是提供在晶体管的电特性的阈值电压可以为正的沟道形成区域中的包括氧化物半导体的晶体管的结构，其是所谓的常关断开关元件， 及其制造方法。 在第一氧化物半导体层上形成具有比第一氧化物半导体层更大的电子亲和力和更小的能隙的第二氧化物半导体层。 此外，形成第三氧化物半导体层以覆盖第二氧化物半导体层的侧表面和顶表面，即，第三氧化物半导体层覆盖第二氧化物半导体层。