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206 条记录 (耗时 0.03 秒)

    Method and apparatus for incorporating a multiplier into an FPGA
    111.
    发明授权
    Method and apparatus for incorporating a multiplier into an FPGA 有权

    公开(公告)号：US06573749B2

    公开(公告)日：2003-06-03

    申请号：US10043958

    申请日：2002-01-08

    申请人： Bernard J. New ,  Steven P. Young

    发明人： Bernard J. New ,  Steven P. Young

    IPC分类号： H03K19177

    CPC分类号： G06F15/7867 ,  G06F7/523 ,  G06F17/5054 ,  H03K19/17732 ,  H03K19/1776

    摘要： One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.

    User configurable on-chip memory system
    113.
    发明授权
    User configurable on-chip memory system 有权
    用户可配置的片上存储系统

    公开(公告)号：US06522167B1

    公开(公告)日：2003-02-18

    申请号：US09757760

    申请日：2001-01-09

    申请人： Ahmad R. Ansari ,  Stephen M. Douglass ,  Mehul R. Vashi ,  Steven P. Young

    发明人： Ahmad R. Ansari ,  Stephen M. Douglass ,  Mehul R. Vashi ,  Steven P. Young

    IPC分类号： G06F738

    CPC分类号： G06F15/7867

    摘要： A data processing system having a user configurable memory controller, one or more block RAMS, and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.

    摘要翻译： 具有用户可配置存储器控制器，一个或多个块RAMS和处理器核的数据处理系统可以被配置在单个现场可编程门阵列（FPGA）中。 块RAM的地址深度和等待状态的数量可以由用户选择，并且可以在FPGA的配置之前设置，也可以使用处理器核心的指令进行编程。 还公开了可以优化地址深度和等待状态数以达到性能水平的算法。 本发明可以应用于具有单独的指令和数据侧的设计。

    Interconnect structure for a programmable logic device
    114.
    发明授权
    Interconnect structure for a programmable logic device 有权

    公开(公告)号：US06448808B2

    公开(公告)日：2002-09-10

    申请号：US09929977

    申请日：2001-08-15

    申请人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

    发明人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

    IPC分类号： H01L2500

    CPC分类号： H03K19/1737 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17796

    摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

    Configurable logic block with AND gate for efficient multiplication in FPGAS
    115.
    发明授权
    Configurable logic block with AND gate for efficient multiplication in FPGAS 失效
    具有与门的可配置逻辑块，用于FPGAS中的高效乘法

    公开(公告)号：US06427156B1

    公开(公告)日：2002-07-30

    申请号：US08786818

    申请日：1997-01-21

    申请人： Kenneth D. Chapman ,  Steven P. Young

    发明人： Kenneth D. Chapman ,  Steven P. Young

    IPC分类号： G06F738

    CPC分类号： H03K19/17728 ,  H03K19/1737 ,  H03K19/17704

    摘要： An improved CLB architecture, wherein the use of dedicated AND gates to generate a carry chain input signal facilitates low latency multiplication and makes efficient use of four-input function generators. In one embodiment of the invention, when multiplication using a binary addition tree algorithm is used, AND gates to implement single-bit multiplication are provided within the available function generators and duplicated in a dedicated AND gate accessible outside the corresponding function generator as a carry-chain input signal. In another embodiment, carry chain multiplexers can be selectively configured as AND or OR gates to facilitate certain arithmetic or comparison functions for the outputs of a plurality of function generators.

    摘要翻译： 一种改进的CLB架构，其中使用专用AND门来产生进位链输入信号有利于低延迟乘法并且有效地使用四输入函数发生器。 在本发明的一个实施例中，当使用使用二进制加法树算法的乘法时，在可用函数发生器内提供用于实现单比特乘法的AND门，并复制到可在对应的函数发生器外面的专用AND门作为进位 - 链输入信号。 在另一个实施例中，进位链多路复用器可以选择性地配置为“与”或“或”门，以促进多个功能发生器的输出的某些算术或比较功能。

    Structure and method for generating a clock enable signal in a PLD
    116.
    发明授权
    Structure and method for generating a clock enable signal in a PLD 有权
    用于在PLD中产生时钟使能信号的结构和方法

    公开(公告)号：US06218864B1

    公开(公告)日：2001-04-17

    申请号：US09370854

    申请日：1999-08-10

    申请人： Steven P. Young ,  Jane W. Sowards ,  Wilson K. Yee

    发明人： Steven P. Young ,  Jane W. Sowards ,  Wilson K. Yee

    IPC分类号： H03K19096

    CPC分类号： H03K19/1774 ,  H03K19/17744

    摘要： The invention provides a structure and method of generating a clock enable signal in a programmable logic device (PLD). A first embodiment of the invention comprises a clock enable circuit implemented such that the critical paths have only two levels of logic. In this embodiment, the critical paths are implemented in dedicated logic while other portions of the clock enable circuit are implemented using programmable logic. According to another embodiment of the invention, the clock enable circuit is located near the center of a first edge of the device. A first plurality of output registers are located along the first edge on either side of the clock enable circuit, with additional output registers being located along the two adjacent half-edges. Programmable interconnection points (PIPs) permit a clock enable interconnect line along the first edge to be programmably extended to the additional output registers. In another embodiment, the clock enable circuit is duplicated in two opposite edges of the device.

    摘要翻译： 本发明提供了一种在可编程逻辑器件（PLD）中产生时钟使能信号的结构和方法。 本发明的第一实施例包括实现为使得关键路径仅具有两个逻辑电平的时钟使能电路。 在本实施例中，关键路径以专用逻辑实现，而使用可编程逻辑实现时钟使能电路的其他部分。 根据本发明的另一实施例，时钟使能电路位于设备的第一边缘的中心附近。 第一组多个输出寄存器位于时钟使能电路两侧的第一边沿，附加的输出寄存器位于两个相邻的半边。 可编程互连点（PIP）允许沿着第一边沿的时钟使能互连线可编程地扩展到附加输出寄存器。 在另一个实施例中，时钟使能电路在设备的两个相对的边缘被复制。

    FPGA configurable by two types of bitstreams
    117.
    发明授权
    FPGA configurable by two types of bitstreams 有权
    FPGA可通过两种类型的比特流进行配置

    公开(公告)号：US06201406B1

    公开(公告)日：2001-03-13

    申请号：US09560451

    申请日：2000-04-28

    申请人： Roman Iwanczuk ,  Steven P. Young

    发明人： Roman Iwanczuk ,  Steven P. Young

    IPC分类号： H03K19173

    CPC分类号： H03K19/17776 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/1776

    摘要： An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer. Using the invention, a bit stream designed for an old device can be used for a new device having additional configuration memory cells.

    摘要翻译： FPGA配置存储器被分成具有唯一地址的柱状帧。 配置数据被加载到配置寄存器中，并且并行传送配置数据。 在优选实施例中，输入寄存器，影子输入寄存器和多路复用器阵列允许使用比常规FPGA更大数量的输入位的有效配置数据传送。 灵活的外部接口使得能够连接到从预定最大宽度到其选定分数的总线大小。 通过使用影子寄存器以最小的延迟逐帧地将这样的数据驱动到存储器单元中，并且通过采用多路复用器阵列来利用更宽的配置数据传输总线，使配置数据传输更有效。 通过采用支持双向数据传输的配置寄存器逻辑，配置回读的速度基本上等于输入配置数据的速率。 使用本发明，为旧设备设计的比特流可以用于具有附加配置存储单元的新设备。

    Structure and method for loading narrow frames of data from a wide input bus
    118.
    发明授权
    Structure and method for loading narrow frames of data from a wide input bus 有权
    用于从宽输入总线加载窄帧数据的结构和方法

    公开(公告)号：US06154048A

    公开(公告)日：2000-11-28

    申请号：US503010

    申请日：2000-02-11

    申请人： Roman Iwanczuk ,  Steven P. Young

    发明人： Roman Iwanczuk ,  Steven P. Young

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/17776 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/1776

    摘要： An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer. Using the invention, a bit stream designed for an old device can be used for a new device having additional configuration memory cells.

    摘要翻译： FPGA配置存储器被分成具有唯一地址的柱状帧。 配置数据被加载到配置寄存器中，并且并行传送配置数据。 在优选实施例中，输入寄存器，影子输入寄存器和多路复用器阵列允许使用比常规FPGA更大数量的输入位的有效配置数据传送。 灵活的外部接口使得能够连接到从预定最大宽度到其选定分数的总线大小。 通过使用影子寄存器以最小的延迟逐帧地将这样的数据驱动到存储器单元中，并且通过采用多路复用器阵列来利用更宽的配置数据传输总线，使配置数据传输更有效。 通过采用支持双向数据传输的配置寄存器逻辑，配置回读的速度基本上等于输入配置数据的速率。 使用本发明，为旧设备设计的比特流可以用于具有附加配置存储单元的新设备。

    High speed bus with tree structure for selecting bus driver
    120.
    发明授权
    High speed bus with tree structure for selecting bus driver 失效
    具有树型结构的高速总线，用于选择公共汽车司机

    公开(公告)号：US5936424A

    公开(公告)日：1999-08-10

    申请号：US950380

    申请日：1997-10-14

    申请人： Steven P. Young ,  Kamal Chaudhary ,  Shekhar Bapat ,  Sridhar Krishnamurthy ,  Philip D. Costello

    发明人： Steven P. Young ,  Kamal Chaudhary ,  Shekhar Bapat ,  Sridhar Krishnamurthy ,  Philip D. Costello

    IPC分类号： H03K19/0175 ,  H03K19/173 ,  H03K19/0185 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  H03K19/017581

    摘要： According to the invention, a structure is provided for driving a bus line that is both fast and small. Instead of a plurality of tristate buffers, one for each input signal, a plurality of multiplexers or gates is connected into a tree structure. The tristate enable line of the tristate buffer becomes the control line for enabling the tree structure to place its own input signal onto the bus instead of propagating the signal already on the bus. A buffer element then allows the resulting signal to be tapped from the bus. One embodiment of the invention includes lookahead logic similar to a lookahead carry chain. This allows large numbers of input lines to be connected to a bus line while retaining high speed. The symmetrical delay of a tree structure minimizes the greatest delay and thus increases predicted speed.

    摘要翻译： 根据本发明，提供一种用于驱动快速且小的总线的结构。 代替多个三态缓冲器，每个输入信号一个，多个多路复用器或门连接到树结构中。 三态缓冲器的三态使能线路成为控制线，用于使树结构能够将其自己的输入信号放置在总线上，而不是传播已经在总线上的信号。 然后，缓冲元件允许从总线中抽出所得到的信号。 本发明的一个实施例包括类似于前瞻携带链的前瞻逻辑。 这允许大量输入线连接到总线，同时保持高速。 树结构的对称延迟使最大延迟最小化，从而增加预测速度。